An Implementation of real-time phased array radar fundamental functions on DSP-focused, high performance embedded computing platform

2016 ◽  
Author(s):  
Xining Yu ◽  
Yan Zhang ◽  
Ankit Patel ◽  
Allen Zahrai ◽  
Mark Weber
Keyword(s):  
Real Time ◽  
High Performance ◽  
Phased Array ◽  
Embedded Computing ◽  
Computing Platform ◽  
Phased Array Radar

scholarly journals An Implementation of Real-Time Phased Array Radar Fundamental Functions on DSP-Focused, High-Performance Embedded Computing Platform

2016 ◽  
Author(s):  
Xining Yu ◽  
Yan Zhang ◽  
Ankit Patel ◽  
Allan Zahrai ◽  
Mark Weber
Keyword(s):  
Real Time ◽  
High Performance ◽  
Pulse Compression ◽  
Phased Array ◽  
Digital Signal ◽  
General Purpose ◽  
Embedded Computing ◽  
Multiple Channel ◽  
Computing Platform ◽  
Phased Array Radar

This paper investigates the feasibility of a backend design for real-time, multiple-channel processing digital phased array system, particularly for high-performance embedded computing platforms constructed of using general purpose digital signal processors. Frist, we obtained the lab-scale backend performance benchmark from simulating beamforming, pulse compression, and Doppler filtering based on MicroTCA chassis using Serial RapidIO protocol in backplane communication. Next, a field-scale demonstrator of a multifunctional phased array radar is emulated by using the similar configuration. Interestingly, the performance of a barebone design is compared to that of emerging tools that systematically take advantage of parallelism and multicore capabilities, including Open Computing Language.

scholarly journals Design and Implementation of Digital Beam Former Architecture for Phased Array Radar

2022 ◽  
Vol 16 ◽  
pp. 9-13
Author(s):  
D. Govind Rao ◽  
N. S. Murthy ◽  
A. Vengadarajan
Keyword(s):  
High Performance ◽  
Phased Array ◽  
Recursive Least Squares ◽  
Echo Signal ◽  
Complex Arithmetic ◽  
Design And Implementation ◽  
Phased Array Radar ◽  
Critical Components ◽  
On Chip ◽  
Very High

This paper deals with the design and implementation of a digital beam former architecture which is developed for 4/8/12/16 element phased array radar. This technique employs a very high performance FPGA to handle large no of parallel complex arithmetic operations including digital down conversion and filtering. A 3MHz echo signal riding on an IF carrier of 60 MHz is under sampled at 50 MHz and down converted digitally to bring the spectrum to echo signal baseband. After suitable decimation filtering, the I and Q channels are multiplied with Recursive Least Squares based optimized complex weights to form partial beams. The prototype architecture employs techniques of pipelining and parallelism to generate multiple beams simultaneously from a 16 element array within 1 μsec. This can be extended to several number of arrays. The critical components employed in this design are eight 16 bit 125 MS/s ADCs and a very high performance state of the art Xilinx FPGA device Virtex-5 FX 130T having several on-chip resources and 150 MHz clock generators.

Sign in / Sign up

Export Citation Format

Share Document