HIGH-SPEED AND HIGH-DATA-BANDWIDTH TRANSMITTER AND RECEIVER FOR MULTI-CHANNEL SERIAL DATA COMMUNICATION WITH CMOS TECHNOLOGY

2001 ◽  
pp. 1-33
Author(s):  
MUNEO FUKAISHI ◽  
KAZUYUKI NAKAMURA ◽  
MICHIO YOTSUYANAGI
Keyword(s):  
High Speed ◽  
Data Communication ◽  
Cmos Technology ◽  
High Data ◽  
Serial Data

HIGH-SPEED AND HIGH-DATA-BANDWIDTH TRANSMITTER AND RECEIVER FOR MULTI-CHANNEL SERIAL DATA COMMUNICATION WITH CMOS TECHNOLOGY

2001 ◽  
Vol 11 (01) ◽  
pp. 1-33
Author(s):  
MUNEO FUKAISHI ◽  
KAZUYUKI NAKAMURA ◽  
MICHIO YOTSUYANAGI
Keyword(s):  
High Speed ◽  
Frequency Conversion ◽  
Data Communication ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Phase Detector ◽  
High Data ◽  
Communication Circuits ◽  
Multiple Receiver ◽  
High Level

This paper briefly reviews recent research on CMOS gigahertz-rate communication circuits and design innovations for overcoming device performance limitations. A multi-channel transmitter and receiver chip set operating at 5 Gb/s has been developed using 0.25-μm CMOS technology. To achieve high-speed operation, the chip set features: (1) a tree-type demultiplexer and frequency conversion architecture, (2) a self-aligning phase detector for clock and data recovery circuit, and (3) a fully pipelined 8-bit to 10-bit encoder. The features contributing to the achievement of high-data bandwidth for multi-channel transmission include circuits for compensating for the phase difference between multiple receiver chips and for the frequency difference between the system clocks of the transmitter and receiver chips. These techniques for high-speed operation and multi-channel transmission are supported by the high level of integration possible with CMOS technology compared with non-CMOS technology.

Dual Monitoring Communication for Self-Aware Network-on-Chip

2012 ◽  
Vol 3 (3) ◽  
pp. 72-91
Author(s):  
Liang Guang ◽  
Ethiopia Nigussie ◽  
Juha Plosila ◽  
Hannu Tenhunen
Keyword(s):  
High Speed ◽  
Data Communication ◽  
Cmos Technology ◽  
Network On Chip ◽  
Time Profile ◽  
Self Awareness ◽  
Monitoring Networks ◽  
Communication Architecture ◽  
Run Time ◽  
On Chip

Self-aware and adaptive Network-on-Chip (NoC) with dual monitoring networks is presented. Proper monitoring interface is an essential prerequisite to adaptive system reconfiguration in parallel on-chip computing. This work proposes a DMC (dual monitoring communication) architecture to support self-awareness on the NoC platform. One type of monitoring communication is integrated with data channel, in order to trace the run-time profile of data communication in high-speed on-chip networking. The other type is separate from the data communication, and is needed to report the run-time profile to the supervising monitor. Direct latency monitoring on mesochronous NoC is presented as a case study and is directly traced in the integrated communication with a novel latency monitoring table in each router. The latency information is reported by the separate monitoring communication to the supervising monitor, which reconfigures the system to adjust the latency, for instance by dynamic voltage and frequency scaling. With quantitative evaluation using synthetic traces and real applications, the effectiveness and efficiency of direct latency monitoring with DMC architecture is demonstrated. The area overhead of DMC architecture is estimated to be small in 65nm CMOS technology.

scholarly journals Improved Precoder Architecture for Duobinary Transceivers

2017 ◽  
Vol 5 ◽  
Author(s):  
Javier Aguirre Olcoz ◽  
C. Sánchez-Azqueta ◽  
E. Guerrero ◽  
C. Gimeno ◽  
S. Celma
Keyword(s):  
Data Transmission ◽  
High Speed ◽  
Cmos Technology ◽  
Modulation Scheme ◽  
Serial Data ◽  
Soi Cmos

Duobinary modulation is an attractive baseband modulation scheme for high-speed serial data transmission. This work presents a duobinary transceiver with a new precoder architecture that overcomes the glitch vulnerability of the conventional ones. It has been fabricated in a 0.13-μm PD-SOI CMOS technology and achieves 10 Gbps consuming 37 mW. 

scholarly journals Terahertz CMOS PA-less Dynamic Optimal Load OOK Modulator for High-Speed Chip-to-Chip Communication

2017 ◽  
Author(s):  
Jason Truman
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Data Rate ◽  
Wireless Data ◽  
High Data ◽  
Dc Power ◽  
Wireless Data Transmission ◽  
Optimal Load ◽  
Artificial Dielectric ◽  
Digitally Controlled

A novel architecture of terahertz CMOS PA-less dynamic optimal load OOK modulator with low loss, high ON/OFF ratio and high data rate while no DC power consumption is proposed. The modulator is simulated in a 28-nm CMOS technology and has 3dB loss, 20dB ON/OFF ratio and 20Gbps data rate with zero DC power by utilizing digitally controlled artificial dielectric (DiCAD). The proposed terahertz modulator helps make possible 20Gbps short-range wireless data transmission at terahertz regime.

Design of Eight Parallel 512-Point MDF FFT/IFFT Processor for WPAN Applications

2019 ◽  
Vol 28 (05) ◽  
pp. 1950088
Author(s):  
C. A. Arun ◽  
Prakasam Periasamy
Keyword(s):  
High Speed ◽  
Supply Voltage ◽  
Complex Multiplication ◽  
Cmos Technology ◽  
Divide And Conquer ◽  
Area Network ◽  
High Data ◽  
Wireless Personal Area Network ◽  
Mixed Approach ◽  
Personal Area Network

This paper presents a high-speed FFT algorithm for high data rate wireless personal area network applications. In a wireless personal area network, the FFT/IFFT block leads the major role. Computational requirements of FFT processors are a heavy burden in most real-time applications. From the previous work, it can be recognized that most of the FFT structures follow the divide and conquer algorithms, which improve the computational efficiency. In the proposed model, a new design of 512-point FFT/IFFT processor is derived by mixed approach for a Radix-26 algorithm, which has been presented and implemented using the Eight Parallel Multipath Delay Feedback (MDF) architecture. In this work, three distinct complex multiplication approaches are derived; from the analysis, a mixed approach has been proposed to reduce the multiplier complexity and also the equivalent normalized area. The proposed design is compiled and simulated with 90[Formula: see text]nm CMOS technology optimized for a 1.2[Formula: see text]V supply voltage. The proposed Mixed Radix-26 algorithm has been verified and validated using existing architectures. It has been found that the proposed mixed approach for Radix-26 algorithm reduces the normalized area by 8.603% compared with verified architectures. Also, the multiplier complexity is reduced by more than 33% using Canonical Signed Digit constant multiplier. The proposed architecture is suitable for applications like OFDM based WPAN applications at high data processing rates.

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