scholarly journals Terahertz CMOS PA-less Dynamic Optimal Load OOK Modulator for High-Speed Chip-to-Chip Communication

2017 ◽  
Author(s):  
Jason Truman
Keyword(s):  
High Speed ◽  
Cmos Technology ◽  
Data Rate ◽  
Wireless Data ◽  
High Data ◽  
Dc Power ◽  
Wireless Data Transmission ◽  
Optimal Load ◽  
Artificial Dielectric ◽  
Digitally Controlled

A novel architecture of terahertz CMOS PA-less dynamic optimal load OOK modulator with low loss, high ON/OFF ratio and high data rate while no DC power consumption is proposed. The modulator is simulated in a 28-nm CMOS technology and has 3dB loss, 20dB ON/OFF ratio and 20Gbps data rate with zero DC power by utilizing digitally controlled artificial dielectric (DiCAD). The proposed terahertz modulator helps make possible 20Gbps short-range wireless data transmission at terahertz regime.

scholarly journals A –5 dBm 400MHz OOK Transmitter for Wireless Medical Application

2014 ◽  
Vol 60 (2) ◽  
pp. 193-198
Author(s):  
M. Yousefi ◽  
D. Koozehkanani ◽  
H. Jangi ◽  
N. Nasirzadeh ◽  
J. Sobhi
Keyword(s):  
Energy Consumption ◽  
Power Amplifier ◽  
High Efficiency ◽  
Medical Application ◽  
Cmos Technology ◽  
High Energy ◽  
Data Rate ◽  
High Data Rate ◽  
Low Power Consumption ◽  
High Data

Abstract A 400 MHz high efficiency transmitter for wireless medical application is presented in this paper. Transmitter architecture with high-energy efficiencies is proposed to achieve high data rate with low power consumption. In the on-off keying transmitters, the oscillator and power amplifier are turned off when the transmitter sends 0 data. The proposed class-e power amplifier has high efficiency for low level output power. The proposed on-off keying transmitter consumes 1.52 mw at -5 dBm output by 40 Mbps data rate and energy consumption 38 pJ/bit. The proposed transmitter has been designed in 0.18μm CMOS technology.

scholarly journals Millimetre-Wave Planar Phased Patch Array with Sidelobe Suppression for High Data-Rate Transmission

2019 ◽  
Vol 2019 ◽  
pp. 1-7
Author(s):  
Hung-Chen Chen ◽  
Tsenchieh Chiu ◽  
Ching-Luh Hsu
Keyword(s):  
Power Distribution ◽  
Phase Shifter ◽  
Radiation Power ◽  
Data Rate ◽  
High Data Rate ◽  
Sidelobe Suppression ◽  
Millimetre Wave ◽  
High Data ◽  
Rate Transmission ◽  
Digitally Controlled

A design of 38 GHz planar phased patch array with sidelobe suppression for data-rate enhancement is proposed in the paper. The proposed array is formed of three 24-element subarrays of patches. Each patch has its own transmit/receive modules (TRM) consisting of a digitally controlled attenuator and phase shifter. In order to achieve high data-rate communications, the noise, especially due to the undesired signals received from the sidelobes, should be reduced with high sidelobe suppression of subarray. The sidelobe suppression of the proposed subarray is first improved to 17.92 dB with a diamond-shaped aperture and then better than 35 dB with a tapered radiation power distribution. The excellent sidelobe suppression of the antenna array is essential for the beam-division multiplexing applications when the signal sources are close to each other. The proposed design is validated experimentally, including the data-rate measurements showing that the 7 Gbps data transmission can be achieved with sufficient sidelobe suppression of the proposed design.

scholarly journals Proactive Forwarding of High Data Rate in Smart Virtualization Networks for High-Speed Trains

2020 ◽  
Vol 14 (2) ◽  
pp. 1670-1681
Author(s):  
Fouad Ali Yaseen ◽  
Hamed S. Al-Raweshidy
Keyword(s):  
High Speed ◽  
Data Rate ◽  
High Data Rate ◽  
High Data ◽  
High Speed Trains

The Evolution of Integrated CMOS Power Amplifiers for Next Generation Mobile Wireless Transceivers

2019 ◽  
Vol 29 (07) ◽  
pp. 2030007
Author(s):  
Selvakumar Mariappan ◽  
Jagadheswaran Rajendran ◽  
Harikrishnan Ramiah ◽  
Norlaili Mohd Noh ◽  
Asrulnizam Abd Manaf
Keyword(s):  
Data Rate ◽  
Integrated System ◽  
High Data Rate ◽  
Wireless Transceivers ◽  
Mobile Wireless ◽  
Fully Integrated ◽  
High Data ◽  
Dc Power ◽  
On Chip ◽  
Frequency Power

Wireless communication standard continues to evolve in order to fulfill the demand for high data rate operation. This leads to the exertion on the design of radio frequency power amplifier (RFPA) which consumes high DC power in order to support linear transmission of high data rate signal. Hence, operating the PA with low DC power consumption without trading-off the linearity is vital in order to achieve the goal of achieving fully integrated system-on-chip (SoC) solution for 4G and 5G transceivers. In this paper, the evolution of CMOS PA toward achieving a fully integrated transceiver solution is discussed through the review of multifarious CMOS PA design. This is categorized into the review of efficiency enhancement designs followed by linearity enhancement designs of the CMOS PA.

Design of DQPSK Demodulator for Implantable Biomedical Devices

2020 ◽  
Vol 29 (11) ◽  
pp. 2020007
Author(s):  
Vaibhav Garg ◽  
Kavindra Kandpal
Keyword(s):  
Low Power ◽  
Carrier Frequency ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Vital Role ◽  
Data Rate ◽  
High Data Rate ◽  
Biomedical Devices ◽  
High Data ◽  
Implantable Biomedical Devices

Implantable biomedical devices (IBDs) play a vital role in today’s healthcare industry. Such applications demand high data rate, low power and small-sized demodulators. This work presents a simple small-sized low-power architecture for differential quadrature phase shift keying (DQPSK) demodulator for these devices. The proposed circuitry is designed in UMC 90-nm CMOS technology and occupies a layout area of 0.015[Formula: see text]mm2. It is operated at 1-V supply voltage with a power consumption of 405[Formula: see text][Formula: see text]W. The carrier frequency is 10[Formula: see text]MHz and the obtained data rate is 20[Formula: see text]Mbps. Hence it exhibits a high data-rate-to-carrier-frequency (DRCF) ratio of 200% making it ideal for IBDs.

HIGH-SPEED AND HIGH-DATA-BANDWIDTH TRANSMITTER AND RECEIVER FOR MULTI-CHANNEL SERIAL DATA COMMUNICATION WITH CMOS TECHNOLOGY

2001 ◽  
Vol 11 (01) ◽  
pp. 1-33
Author(s):  
MUNEO FUKAISHI ◽  
KAZUYUKI NAKAMURA ◽  
MICHIO YOTSUYANAGI
Keyword(s):  
High Speed ◽  
Frequency Conversion ◽  
Data Communication ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Phase Detector ◽  
High Data ◽  
Communication Circuits ◽  
Multiple Receiver ◽  
High Level

This paper briefly reviews recent research on CMOS gigahertz-rate communication circuits and design innovations for overcoming device performance limitations. A multi-channel transmitter and receiver chip set operating at 5 Gb/s has been developed using 0.25-μm CMOS technology. To achieve high-speed operation, the chip set features: (1) a tree-type demultiplexer and frequency conversion architecture, (2) a self-aligning phase detector for clock and data recovery circuit, and (3) a fully pipelined 8-bit to 10-bit encoder. The features contributing to the achievement of high-data bandwidth for multi-channel transmission include circuits for compensating for the phase difference between multiple receiver chips and for the frequency difference between the system clocks of the transmitter and receiver chips. These techniques for high-speed operation and multi-channel transmission are supported by the high level of integration possible with CMOS technology compared with non-CMOS technology.

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