Data Mapping and Financial Dashboards

2016 ◽  
pp. 641-663
Author(s):  
Ai Wen WONG
Keyword(s):  
2021 ◽  
Vol 11 (14) ◽  
pp. 6486
Author(s):  
Mei-Ling Chiang ◽  
Wei-Lun Su

NUMA multi-core systems divide system resources into several nodes. When an imbalance in the load between cores occurs, the kernel scheduler’s load balancing mechanism then migrates threads between cores or across NUMA nodes. Remote memory access is required for a thread to access memory on the previous node, which degrades performance. Threads to be migrated must be selected effectively and efficiently since the related operations run in the critical path of the kernel scheduler. This study focuses on improving inter-node load balancing for multithreaded applications. We propose a thread-aware selection policy that considers the distribution of threads on nodes for each thread group while migrating one thread for inter-node load balancing. The thread is selected for which its thread group has the least exclusive thread distribution, and thread members are distributed more evenly on nodes. This has less influence on data mapping and thread mapping for the thread group. We further devise several enhancements to eliminate superfluous evaluations for multithreaded processes, so the selection procedure is more efficient. The experimental results for the commonly used PARSEC 3.0 benchmark suite show that the modified Linux kernel with the proposed selection policy increases performance by 10.7% compared with the unmodified Linux kernel.


Author(s):  
Yongjoo Kim ◽  
Jongeun Lee ◽  
A. Shrivastava ◽  
J. W. Yoon ◽  
Doosan Cho ◽  
...  

2013 ◽  
Vol 680 ◽  
pp. 534-539
Author(s):  
Wei Feng Ma

With the rapid expansion of the campus scale and the increasing of the geographically dispersed campus, how to adopt new theory, new method and new technology to realize the equipment optimized assignment and the information management is a new research challenge. It is the key to safeguard the national fund to use reasonably, and to speed up the development of education healthily. Through analyzing the domestic and foreign related research works, the paper proposed that it can take use of the spatial data expression and analysis with Geographic Information System (GIS) to realize the large-scale and inter-campuses equipment optimized assignment and information management. It discussed the mathematics model and the system architecture. Moreover, the paper described the key implementation technology in great detail such as spatial data mapping with MapInfo professional 9 and the development of WebGIS functions with MapXtreme. The results show that the solution is feasible and effective.


Author(s):  
Ping Yi ◽  
Bin Ran

This research examines a streamlined accident data acquisition, communications, and analysis system to improve the Chinese highway safety program. A data logger compatible with the Global Positioning System and geographic information system is proposed to identify highway accident locations and organize the data into a database format. A data encoding concept is used to transform Chinese characters into numbers, so that the encoded data are easy to integrate into a large data system. A three-tier client–server networking system is set up as the backbone framework for data communications between the central database and distributed local offices. Using local database functions, traffic police at the client level can view crash data through data mapping and attribute listing and analyze the data through nested query and sorting operations. A data graphing and analysis module was tested for automatically constructing a collision diagram on selected data. The proposed approach to crash data acquisition and analysis was found to be feasible and effective and will help to enhance China’s highway safety program after full implementation.


Author(s):  
Eduardo H. M. Cruz ◽  
Matthias Diener ◽  
Laércio L. Pilla ◽  
Philippe O. A. Navaux

Current and future architectures rely on thread-level parallelism to sustain performance growth. These architectures have introduced a complex memory hierarchy, consisting of several cores organized hierarchically with multiple cache levels and NUMA nodes. These memory hierarchies can have an impact on the performance and energy efficiency of parallel applications as the importance of memory access locality is increased. In order to improve locality, the analysis of the memory access behavior of parallel applications is critical for mapping threads and data. Nevertheless, most previous work relies on indirect information about the memory accesses, or does not combine thread and data mapping, resulting in less accurate mappings. In this paper, we propose the Sharing-Aware Memory Management Unit (SAMMU), an extension to the memory management unit that allows it to detect the memory access behavior in hardware. With this information, the operating system can perform online mapping without any previous knowledge about the behavior of the application. In the evaluation with a wide range of parallel applications (NAS Parallel Benchmarks and PARSEC Benchmark Suite), performance was improved by up to 35.7% (10.0% on average) and energy efficiency was improved by up to 11.9% (4.1% on average). These improvements happened due to a substantial reduction of cache misses and interconnection traffic.


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