MATERIALS FOR STRAINED SILICON DEVICES

Strained Si devices exhibit enhanced carrier mobility compared to that of standard Si CMOS devices of the same dimensions. Recent strained Si CMOS device results are reviewed. Materials issues related to the strained Si/relaxed SiGe heterostructures required for a strained Si CMOS technology are discussed.

Download Full-text

Nanoscale Heat Conduction in the SOI, Strained-Si and Tri-Gate Transistors

Design, Synthesis, and Applications ◽

10.1115/nano2004-46050 ◽

2004 ◽

Author(s):

Mehdi Asheghi

Keyword(s):

Carrier Mobility ◽

High Mobility ◽

Silicon On Insulator ◽

Strained Silicon ◽

Device Performance ◽

Strained Si ◽

Insulator Layer ◽

Junction Capacitance ◽

Induced Changes ◽

Soi Technology

There have been many attempts in the recent years to improve the device performance by enhancing carrier mobility by using the strained-induced changes in silicon electronic bands [1–4] or reducing the junction capacitance in silicon-on-insulator (SOI) technology. Strained silicon on insulator (SSOI) is another promising technology, which is expected to show even higher performance, in terms of speed and power consumption, comparing to the regular strained-Si transistors. In this technology, the strained silicon is incorporated in the silicon on insulator (SOI) technology such that the strained-Si introduces high mobility for electrons and holes and the insulator layer (usually SiO2) exhibits low junction capacitance due to its small dielectric constant [5, 6]. In these devices a layer of SiGe may exist between the strined-Si layer and insulator (strained Si-on-SiGe-on-insulator, SGOI) [6] or the strained-Si layer can be directly on top of the insulator [7]. Latter is advantageous for eliminating some of the key problems associated with the fabrication of SGOI.

Download Full-text

The Role of Preamorphization and Activation for Ultra Shallow Junction Formation on Strained Si Layers Grown on SiGe Buffer

MRS Proceedings ◽

10.1557/proc-809-b9.6.1/c9.6 ◽

2004 ◽

Vol 809 ◽

Author(s):

B.J. Pawlak ◽

W. Vandervorst ◽

R. Lindsay ◽

I. De Wolf ◽

F. Roozeboom ◽

...

Keyword(s):

Carrier Mobility ◽

Solid Phase ◽

Cmos Technology ◽

Strained Si ◽

Transistor Channel ◽

Thermal Budget ◽

Dopant Activation ◽

Junction Formation ◽

Technology Nodes

In advanced CMOS technology nodes one may achieve further enhancement of device performance by carrier mobility modification in the transistor channel. The carrier mobility enhancement can be realized by formation of strained silicon layers on a Si1−xGex strain relaxed buffer. Formation of source and drain extensions on such structures need to satisfy one additional requirement, the formation process, including the activation related thermal budget should not relax the strain in the channel. In this paper we separately investigate the role of amorphization during implantation, different doping impurities and thermal budget on the junction and the transistor channel regions properties. Two approaches of dopant activation are discussed: low temperature solid phase epitaxial regrowth and high temperature conventional spike.

Download Full-text

On the influence of interface charging dynamics and stressing conditions in strained silicon devices

Scientific Reports ◽

10.1038/s41598-017-05067-9 ◽

2017 ◽

Vol 7 (1) ◽

Cited By ~ 5

Author(s):

Irene Olivares ◽

Todora Angelova ◽

Pablo Sanchis

Keyword(s):

Strained Silicon ◽

Silicon Devices ◽

Charging Dynamics

Download Full-text

First-principles study of electronic properties of biaxially strained silicon: Effects on charge carrier mobility

Physical Review B ◽

10.1103/physrevb.78.245204 ◽

2008 ◽

Vol 78 (24) ◽

Cited By ~ 59

Author(s):

Decai Yu ◽

Yu Zhang ◽

Feng Liu

Keyword(s):

Charge Carrier ◽

Electronic Properties ◽

First Principles ◽

Carrier Mobility ◽

Charge Carrier Mobility ◽

Strained Silicon ◽

First Principles Study

Download Full-text

Layout level timing optimization by leveraging active area dependent mobility of strained-silicon devices

2008 Design, Automation and Test in Europe ◽

10.1145/1403375.1403582 ◽

2008 ◽

Cited By ~ 1

Author(s):

Ashutosh Chakraborty ◽

Sean X. Shi ◽

David Z. Pan

Keyword(s):

Active Area ◽

Strained Silicon ◽

Timing Optimization ◽

Silicon Devices

Download Full-text

Strained-Si CMOS Technology

Advanced Microelectronics - Advanced Gate Stacks for High-Mobility Semiconductors ◽

10.1007/978-3-540-71491-0_1 ◽

2007 ◽

pp. 1-19 ◽

Cited By ~ 6

Author(s):

S. Takagi

Keyword(s):

Cmos Technology ◽

Strained Si

Download Full-text

Thick-Strained-Si/SiGe CMOS Technology with Selective-Epitaxial-Si Shallow-Trench Isolation (SES-STI)

2006 International SiGe Technology and Device Meeting ◽

10.1109/istdm.2006.1662552 ◽

2006 ◽

Author(s):

M. Miyamoto ◽

N. Sugii ◽

Y. Yoshida ◽

Y. Hoshino ◽

Y. Kimura ◽

...

Keyword(s):

Cmos Technology ◽

Strained Si ◽

Shallow Trench Isolation ◽

Trench Isolation

Download Full-text

Strained Silicon On Insulator wafers made by the Smart Cut™ technology

MRS Proceedings ◽

10.1557/proc-809-b2.3 ◽

2004 ◽

Vol 809 ◽

Cited By ~ 1

Author(s):

B. Ghyselen ◽

Y. Bogumilowicz ◽

C. Aulnette ◽

A. Abbadie ◽

B. Osternaud ◽

...

Keyword(s):

Thin Films ◽

Hole Mobility ◽

Silicon On Insulator ◽

Strained Silicon ◽

Layer Transfer ◽

Strained Si ◽

Engineered Substrates

ABSTRACTStrained Silicon On Insulator wafers are today envisioned as a natural and powerfulenhancement to standard SOI and/or bulk-like strained Si layers. For MOSFETs applications, thisnew technology potentially combines enhanced devices scalability allowed by thin films andenhanced electron and hole mobility in strained silicon. This paper is intended to demonstrate byexperimental results how a layer transfer technique such as the Smart Cut™ technology can be usedto obtain good quality tensile Strained Silicon On insulator wafers. Detailed experiments andcharacterizations will be used to characterize these engineered substrates and show that they arecompatible with the applications.

Download Full-text