Nanoscale Heat Conduction in the SOI, Strained-Si and Tri-Gate Transistors

2004 ◽  
Author(s):  
Mehdi Asheghi
Keyword(s):  
Carrier Mobility ◽  
High Mobility ◽  
Silicon On Insulator ◽  
Strained Silicon ◽  
Device Performance ◽  
Strained Si ◽  
Insulator Layer ◽  
Junction Capacitance ◽  
Induced Changes ◽  
Soi Technology

There have been many attempts in the recent years to improve the device performance by enhancing carrier mobility by using the strained-induced changes in silicon electronic bands [1–4] or reducing the junction capacitance in silicon-on-insulator (SOI) technology. Strained silicon on insulator (SSOI) is another promising technology, which is expected to show even higher performance, in terms of speed and power consumption, comparing to the regular strained-Si transistors. In this technology, the strained silicon is incorporated in the silicon on insulator (SOI) technology such that the strained-Si introduces high mobility for electrons and holes and the insulator layer (usually SiO2) exhibits low junction capacitance due to its small dielectric constant [5, 6]. In these devices a layer of SiGe may exist between the strined-Si layer and insulator (strained Si-on-SiGe-on-insulator, SGOI) [6] or the strained-Si layer can be directly on top of the insulator [7]. Latter is advantageous for eliminating some of the key problems associated with the fabrication of SGOI.

Strained Silicon On Insulator wafers made by the Smart Cut™ technology

2004 ◽  
Vol 809 ◽  
Author(s):  
B. Ghyselen ◽  
Y. Bogumilowicz ◽  
C. Aulnette ◽  
A. Abbadie ◽  
B. Osternaud ◽  
...  
Keyword(s):  
Thin Films ◽  
Hole Mobility ◽  
Silicon On Insulator ◽  
Strained Silicon ◽  
Layer Transfer ◽  
Strained Si ◽  
Engineered Substrates

ABSTRACTStrained Silicon On Insulator wafers are today envisioned as a natural and powerfulenhancement to standard SOI and/or bulk-like strained Si layers. For MOSFETs applications, thisnew technology potentially combines enhanced devices scalability allowed by thin films andenhanced electron and hole mobility in strained silicon. This paper is intended to demonstrate byexperimental results how a layer transfer technique such as the Smart Cut™ technology can be usedto obtain good quality tensile Strained Silicon On insulator wafers. Detailed experiments andcharacterizations will be used to characterize these engineered substrates and show that they arecompatible with the applications.

Photoluminescence study of an ultrathin strained silicon on insulator layer

2007 ◽  
Vol 90 (4) ◽  
pp. 042110 ◽  
Author(s):  
J. Munguía ◽  
G. Bremond ◽  
J. de la Torre ◽  
J.-M. Bluet
Keyword(s):  
Silicon On Insulator ◽  
Strained Silicon ◽  
Insulator Layer ◽  
Photoluminescence Study

Carrier mobility degradation due to high dose implantation in ultrathin unstrained and strained silicon-on-insulator films

2007 ◽  
Vol 102 (10) ◽  
pp. 104505 ◽  
Author(s):  
C. Dupré ◽  
T. Ernst ◽  
J.-M. Hartmann ◽  
F. Andrieu ◽  
J.-P. Barnes ◽  
...  
Keyword(s):  
Carrier Mobility ◽  
Silicon On Insulator ◽  
Strained Silicon ◽  
High Dose ◽  
Mobility Degradation ◽  
High Dose Implantation

MATERIALS FOR STRAINED SILICON DEVICES

2002 ◽  
Vol 12 (02) ◽  
pp. 305-314 ◽  
Author(s):  
P. M. MOONEY
Keyword(s):  
Carrier Mobility ◽  
Cmos Technology ◽  
Strained Silicon ◽  
Strained Si ◽  
Silicon Devices

Strained Si devices exhibit enhanced carrier mobility compared to that of standard Si CMOS devices of the same dimensions. Recent strained Si CMOS device results are reviewed. Materials issues related to the strained Si/relaxed SiGe heterostructures required for a strained Si CMOS technology are discussed.

Temperature dependence of the indirect bandgap in ultrathin strained silicon on insulator layer

2012 ◽  
Vol 100 (10) ◽  
pp. 102107 ◽  
Author(s):  
J. Munguía ◽  
J.-M. Bluet ◽  
O. Marty ◽  
G. Bremond ◽  
M. Mermoux ◽  
...  
Keyword(s):  
Temperature Dependence ◽  
Silicon On Insulator ◽  
Strained Silicon ◽  
Insulator Layer

Measurement of the residual macro and microstrain in strained Si/SiGe using Raman spectroscopy

2004 ◽  
Vol 809 ◽  
Author(s):  
P. Dobrosz ◽  
S.J. Bull ◽  
S.H. Olsen ◽  
A.G. O'Neill
Keyword(s):  
Raman Spectroscopy ◽  
Silicon Germanium ◽  
Peak Shift ◽  
Peak Position ◽  
Laser Raman Spectroscopy ◽  
Strained Silicon ◽  
Device Performance ◽  
Extended Defects ◽  
Strained Si ◽  
Laser Raman

ABSTRACTThe use of laser Raman spectroscopy to assess the residual strain in strained silicon/silicon germanium devices is well established. The peak shift associated with the 520cm−1 silicon peak can be used to directly measure the strain in the cap layer provided that the strained silicon peak can be deconvoluted from the more intense Si in SiGe peak which occurs at slightly lower wavenumbers. However, though peak position gives a measure of the macrostrains in the layer it is not useful for the assessment of microstrains associated with point defects which may also influence device performance; such microstrains influence the intensity of the Raman peaks and can, in principle, be monitored by this method. In this study we have undertaken a study of peak shape as a function of processing conditions for strained silicon on SiGe. Changes in peak position may be correlated with macrostrains and macrostrain relaxation around extended defects such as dislocations. Changes in peak width can be correlated with processes which lead to changes in composition (e.g. germanium build-up in the surface after etching) and microstrain. Such changes are not necessarily correlated with changes in macrostrain but indicate that microstrain could also be an important factor influencing device performance.

Low temperature mobility improvement in high-mobility strained-Si/Si1-xGex multilayer MOSFETs

1998 ◽  
Vol 08 (PR3) ◽  
pp. Pr3-57-Pr3-60
Author(s):  
J. B. Roldán ◽  
F. Gámiz ◽  
J. A. López-Villanueva ◽  
J. E. Carceller
Keyword(s):  
Low Temperature ◽  
High Mobility ◽  
Strained Si

Application of FIB Circuit Edit in Analysis of Memory Failure of SOI Devices

2006 ◽  
Author(s):  
Z. G. Song ◽  
S. K. Loh ◽  
X. H. Zheng ◽  
S.P. Neo ◽  
C. K. Oh
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Silicon On Insulator ◽  
First Case ◽  
Edx Analyses ◽  
Memory Failure ◽  
Soi Devices ◽  
Voltage Contrast ◽  
Soi Technology

Abstract This article presents two cases to demonstrate the application of focused ion beam (FIB) circuit edit in analysis of memory failure of silicon on insulator (SOI) devices using XTEM and EDX analyses. The first case was a single bit failure of SRAM units manufactured with 90 nm technology in SOI wafer. The second case was the whole column failure with a single bit pass for a SRAM unit. From the results, it was concluded that FIB circuit edit and electrical characterization is a good methodology for further narrowing down the defective location of memory failure, especially for SOI technology, where contact-level passive voltage contrast is not suitable.

LOW-NOISE SILICON-ON-INSULATOR HALL DEVICES

2004 ◽  
Vol 04 (02) ◽  
pp. L345-L354 ◽  
Author(s):  
Y. HADDAB ◽  
V. MOSSER ◽  
M. LYSOWEC ◽  
J. SUSKI ◽  
L. DEMEUS ◽  
...  
Keyword(s):  
Noise Level ◽  
Low Voltage ◽  
Silicon Layer ◽  
Electrical Current ◽  
Low Noise ◽  
Silicon On Insulator ◽  
Technological Parameters ◽  
Wide Range ◽  
Hall Sensors ◽  
Soi Technology

Hall sensors are used in a very wide range of applications. A very demanding one is electrical current measurement for metering purposes. In addition to high precision and stability, a sufficiently low noise level is required. Cost reduction through sensor integration with low-voltage/low-power electronics is also desirable. The purpose of this work is to investigate the possible use of SOI (Silicon On Insulator) technology for this integration. We have fabricated SOI Hall devices exploring the useful range of silicon layer thickness and doping level. We show that noise is influenced by the presence of LOCOS and p-n depletion zones near the edges of the active zones of the devices. A proper choice of SOI technological parameters and process flow leads to up to 18 dB reduction in Hall sensor noise level. This result can be extended to many categories of devices fabricated using SOI technology.

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