Quantum Dot Floating Gate Nonvolatile Random Access Memory Using Ge Quantum Dot Channel for Faster Erasing

2018 ◽  
Vol 27 (01n02) ◽  
pp. 1840006
Author(s):  
Murali Lingalugari ◽  
Evan Heller ◽  
Barath Parthasarathy ◽  
John Chandy ◽  
Faquir Jain
Keyword(s):  
Quantum Dot ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Floating Gate ◽  
Access Memory ◽  
Access Channel ◽  
Ge Quantum Dot ◽  
Long Channel ◽  
Lower Voltage

This paper presents an approach to enhance floating gate quantum dot nonvolatile random access memory (QDNVRAM) cells in terms of higher-speed and lower-voltage Erase not possible with conventional floating gate nonvolatile memories. It is achieved by directly accessing the floating gate layer with a Ge quantum dot access channel via an additional drain (D2) during the Erase and/or Write operation. Quantum mechanical simulations in GeOx-cladded Ge quantum dot layers functioning as the floating gate as well access channel to facilitate Erase and Write are presented. Experimental data on fabricated long channel nonvolatile random access memory cell with SiOx-cladded Si dots is presented. Quantum simulations show lower voltage operation for GeOx-cladded Ge QD floating gate than SiOx-cladded Si dots. The Erase time is orders of magnitude faster than flash and is comparable to competing NVRAMs.

Multi-Bit NVRAMs Using Quantum Dot Gate Access Channel

2017 ◽  
Vol 26 (03) ◽  
pp. 1740014
Author(s):  
Murali Lingalugari ◽  
Pik-Yiu Chan ◽  
John Chandy ◽  
Evan Heller ◽  
Faquir Jain
Keyword(s):  
Quantum Dot ◽  
Random Access ◽  
Random Access Memory ◽  
Floating Gate ◽  
Access Memory ◽  
Storage And Retrieval ◽  
Access Channel ◽  
Array Architecture ◽  
Simulation Results ◽  
Long Channel

This paper presents a quantum dot access channel nonvolatile random access memory (QDAC-NVRAM) which has comparable write and erase times to conventional random access memories but consumes less power and has a smaller footprint. We have fabricated long-channel (W/L=15μm/10μm) nonvolatile random access memories (NVRAMs) with 4μs erase times. These devices are CMOS-compatible and employ novel quantum dot access channel (QDAC) which enables fast storage and retrieval of charge from the floating gate layer. In addition, QDNVRAMs are shown to be capable of storing multiple-bits and potentially scalable to sub 22nm. We are also presenting the simulation results. This paper also presents a memory array architecture using QDAC-NVRAMs.

A Novel Peripheral Circuit for SWSFET Based Multivalued Static Random-Access Memory

2020 ◽  
Vol 29 (01n04) ◽  
pp. 2040010
Author(s):  
R. H. Gudlavalleti ◽  
B. Saman ◽  
R. Mays ◽  
Evan Heller ◽  
J. Chandy ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Quantum Well ◽  
Field Effect Transistors ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Input Gate ◽  
Reduction In Area

This paper presents the peripheral circuitry for a multivalued static random-access memory (SRAM) based on 2-bit CMOS cross-coupled inverters using spatial wavefunction switched (SWS) field effect transistors (SWSFETs). The novel feature is a two quantum well/quantum dot channel n-SWSFET access transistor. The reduction in area with four-bit storage-per-cell increases the memory density and efficiency of the SRAM array. The SWSFET has vertically stacked two-quantum well/quantum dot channels between the source and drain regions. The upper or lower quantum charge locations in the channel region is based on the input gate voltage. The analog behavioral modeling (ABM) of the SWSFET device is done using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit simulations for the proposed memory cell and addressing/peripheral circuitry are presented.

scholarly journals Pre-Emphasis Pulse Design for Random-Access Memory

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1454
Author(s):  
Yoshihiro Sugiura ◽  
Toru Tanzawa
Keyword(s):  
Time Constant ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Memory Access ◽  
Access Time ◽  
Access Memory ◽  
Delay Times ◽  
Cell Current ◽  
The Impact

This paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact of the process variation in the time constant of WL, the cell current, and the resistance of deciding path on optimum PE pulses are discussed. Optimum PE pulse widths and resultant minimum WL delay times are modeled with fitting curves as a function of column address of the accessed memory cell, which provides designers with the ability to set the optimum timing for WL and BL (bit-line) operations, reducing average memory access time.

Temperature Dependence of Phase-Change Random Access Memory Cell

2006 ◽  
Vol 45 (5A) ◽  
pp. 3955-3958 ◽  
Author(s):  
X. S. Miao ◽  
L. P. Shi ◽  
H. K. Lee ◽  
J. M. Li ◽  
R. Zhao ◽  
...  
Keyword(s):  
Phase Change ◽  
Temperature Dependence ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Access Memory
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