Real-time tracking of the self-assembled growth of a 3D Ge quantum dot lattice in an alumina matrix

A laboratory in situ grazing-incidence small-angle X-ray scattering (GISAXS) tracking of the self-assembled growth of a regular 3D Ge quantum dot (QD) structure in an amorphous Al2O3 matrix during the ion beam sputter deposition of a periodic Ge/Al2O3 multilayer on silicon is reported. A 573 K substrate temperature proved to be necessary to achieve the self-assembly effect. Relying on a fast repeated acquisition of GISAXS patterns, the temporal evolution of the growing 3D Ge QD structure was analyzed bilayer by bilayer to determine its type, lateral and vertical correlation lengths, and inter-QD distance. The QD structure was found to have body-centered tetragonal lattice type with ABA stacking, with the lattice parameters refined by fitting the final GISAXS pattern relying on a paracrystal model. A single set of paracrystal parameters enables one to simulate the temporal evolution of the in situ GISAXS patterns throughout the deposition process, suggesting that the Ge QD self-assembly is driven from the very beginning solely by the growing surface morphology. Ex situ GISAXS and X-ray reflectivity measurements along with a cross-section high-resolution transmission electron microscopy analysis complete the study.

Modeling of Quantum Dot Channel (QDC) Si FETs at Sub-Kelvin for Multi-State Logic

Multi-state room temperature operation of SiOx-cladded Si quantum dots (QD) and GeOx-cladded Ge quantum dot channel (QDC) field-effect transistors (FETs) and spatial wavefunction switched (SWS)-FETs have been experimentally demonstrated. This paper presents simulation of cladded Si and Ge quantum dot channel (QDC) field-effect transistors at 4.2°K and milli-Kelvin temperatures. An array of thin oxide barrier/cladding (∼1nm) on quantum dots forms a quantum dot superlattice (QDSL). A gradual channel approximation model using potential and inversion layer charge density nQM, obtained by the self-consistent solution of the Schrodinger and Poisson’s equations, is shown to predict I-V characteristics up to milli-Kelvin temperatures. Physics-based equivalent circuit models do not work below 53°K. However, they may be improved by adapting parameters derived from quantum simulations. Low-temperature operation improves noise margins in QDC- and SWS-FET based multi-bit logic, which dissipates lower power and comprise of fewer device count. In addition, the role of self-assembled cladded QDs with transfer gate provides a novel pathway to implement qubit processing.

3-D Confined SWS-FETs Combining Quantum Well and Quantum Dot Superlattice (QDSL)

Quantum confinement in 3-D leads to novel multi-state larger fan-out carrier transport in quantum dot FETs. Single electron transistors (SETs) and quantum cell automata (QCA) devices are limited by the number of carriers in the transport channel, which affects the logic fan-out in sub-5nm integrated circuits. This paper presents several transport channel structures for overcoming this limitation. Layers with large bandgap discontinuities are used to confine carriers along channel length, between source and drain. These layers are formed with low energy gap Ge QDSLs and are used in several two-channel twin-drain n- and p-FETs in SWS configurations: (i) p-FET with coupled SiGe Quantum well (QW) and Ge Quantum Dot Superlattice (QDSL) channel, (ii) n-FET with upper and lower Ge QDSL channels, and (iii) p-FET with upper and lower Ge QDSL channels on n-on-pSi. The coupling of QW and QDSL channels or two Ge QDSL channels, in a spatial wavefunction switched (SWS) FET structure, not only ensures higher concentration of carriers but also multi-state/multi-bit operation. Circuit simulations of 2-bit NOR gate have used BSIM based analog behavioral model (ABM).

Modeling of Multi-State Si and Ge Cladded Quantum Dot Gate FETs Using Verilog and ABM Simulations

Quantum dot gate (QDG) field-effect transistors (FETs) fabricated using Si and Ge quantum dot layers, self-assembled in the gate region over the tunnel oxide, have exhibited 3- and 4-state behavior applicable for ternary and quaternary logic, respectively. This paper presents simulation of QDG-FETs comprising mixed Ge and Si quantum dot layers over tunnel oxide using an analog behavior model (ABM) and Verilog model. The simulations reproduce the experimental I-V characteristics of a fabricated mixed dot QDG-FET. GeOx-cladded Ge quantum dot layer is in interface to the tunnel oxide and is deposited over with a SiOx-cladded Si quantum dot layer. The fabricated QDG-FET has one source and one gate. The ABM simulation models QDG-FET using conventional BSIM 3V3 FETs with capacitances and other device parameters. In addition, VERILOG model is presented. The agreement in circuit and quantum simulations and experimental data will further advance in the designing of QDG-FET-based analog-to-digital converters (ADCs), 2-bit logic gates and SRAM cells.