A STATIC EXECUTION MODEL FOR DATA PARALLELISM
1994 ◽
Vol 04
(04)
◽
pp. 367-378
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Keyword(s):
A Priori
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The performance of parallel architectures are limited at least as much by data transfer ability as by computing power. The main limit concerns the transfers on the interconnection network. But it becomes apparent that a majority of these communications can be known at compile time. The static model intends to exploit this a priori knowledge in order to drastically reduce the overhead of message passing, the ultimate goal being to confine the oommunication delays to the hardware propagation delays. In the paper, we present an abstract machine which is the target of a static-oriented compilation. We show how to recognize and sequence the static communication patterns, and we discuss the application scope of the model.
2021 ◽
Vol 08
(03)
◽
pp. 01-15
2015 ◽
Vol 8
(10)
◽
pp. 8981-9020
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Keyword(s):
Keyword(s):
2001 ◽
Vol 02
(03)
◽
pp. 345-364
◽
2013 ◽
Vol 133
(5)
◽
pp. 3614-3614
Keyword(s):