scholarly journals A Multifunctional Unit For Reverse Conversion and Sign Detection Based on The 5-Moduli Set

2021 ◽  
Vol 22 (1) ◽  
Author(s):  
Mohsen Mojahed ◽  
Amir Sabbagh Molahosseini ◽  
Azadeh Alsadat Emrani Zarandi

The high dynamic range residue number system (RNS) five-moduli { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 } has been recently introduced as an arithmetically balanced five-moduli set for computation-intensive applications on wide operands such as asymmetric cryptography algorithms. The previous dedicated design of RNS components for this moduli set is just an unsigned reverse converter. In order to utilize of the moduli set { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 } in applications handling with signed numbers, two important components are needed: Sign Detector and Signed Reverse Converter. However, having both of these components results in high hardware requirements which makes RNS impractical. This paper overcomes to this problem by designing a unified unit which can perform both signed reverse conversion as well as sign detection through the reuse of hardware. To the authors knowledge, this is the first attempt to design sign detector for a moduli set including 2n±3 moduli. In order to achieve a hardware-amenable design, we first improved the performance of the previous unsigned reverse converter for the moduli set { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 }. Then, we extract a sign detection method from the structure of the reverse converter. Finally, we make the unsigned reverse converter to sign converter through the use of the extracted sign signal from the reverse converter. The experimental results shown that the proposed multifunctional unit has relatively the same performance in terms of area, delay and power-consumption than the previous unsigned reverse converter for the set { 2 2n , 2 n + 1, 2 n − 1, 2 n + 3, 2 n − 3 } while it can perform two complex signed operations.

2018 ◽  
Vol 27 (05) ◽  
pp. 1850075 ◽  
Author(s):  
Ritesh Kumar Jaiswal ◽  
Raj Kumar ◽  
Ram Awadh Mishra

The efficiency of residue number system depends on the reverse converter due to several modulo operations like addition, subtraction and multiplication. In this paper, a design of new four moduli set [Formula: see text], reverse converter is presented. The moduli set have moduli with length ranging from ([Formula: see text]) to ([Formula: see text])-bits. The reverse conversion for moduli set [Formula: see text] has been optimized in existing state of art. Thus, proposed converter is based on two new moduli set [Formula: see text] and utilizes the mixed radix conversion. This converter is memoryless, and occupies least area. The proposed converter is based on carry save adder (CSA) and modulo adder enabling more speed and less hardware complexity for dynamic range of [Formula: see text]-bit, offering good area-delay product.


2020 ◽  
Vol 29 (11) ◽  
pp. 2030008
Author(s):  
Raj Kumar ◽  
Ritesh Kumar Jaiswal ◽  
Ram Awadh Mishra

Modulo multiplier has been attracting considerable attention as one of the essential components of residue number system (RNS)-based computational circuits. This paper contributes a comprehensive review in the design of modulo [Formula: see text] multipliers for the first time. The modulo multipliers can be implemented using ROM (look-up-table) as well as VLSI components (memoryless); however, the former is preferable for lower word-length and later for larger word-length. The modular and parallelism properties of RNS are used to improve the performance of memoryless multipliers. Moreover, a Booth-encoding algorithm is used to speed-up the multipliers. Also, an advanced modulo [Formula: see text] multiplier based on redundant RNS (RRNS) could be further chosen for very high dynamic range. These perspectives of modulo [Formula: see text] multipliers have been extensively studied for recent state-of-the-art and analyzed using Synopsis design compiler tool.


2000 ◽  
Vol 10 (01n02) ◽  
pp. 85-99 ◽  
Author(s):  
A. P VINOD ◽  
A. BENJAMIN PREMKUMAR

This paper presents a residue number system to binary converter in the four moduli set {2n - 1, 2n, 2n + 1, 2n + 1 - 1}, valid for even values of n. This moduli set is an extension of the popular set {2n - 1, 2n + 1}. The number theoretic properties of the moduli set of the form 2n ± 1 are exploited to design the converter. The main challenge of dealing with fractions in Residue Number System is overcome by using the fraction compensation technique. A hardware implementation using only adders is also proposed. When compared to the common three moduli reverse converters, this four moduli converter offers a larger dynamic range and higher parallelism, which makes it useful for high performance computing.


2011 ◽  
Vol 24 (1) ◽  
pp. 89-103
Author(s):  
Negovan Stamenkovic ◽  
Bojan Jovanovic

The residue number system (RNS) is an integer system capable of supporting high speed concurrent arithmetic. One of the most important consideration when designing RNS system is reverse conversion. The reverse converter for recently proposed for the four-moduli set {2? -1,2?, 2? +1,2??+? -1} is based on new Chinese remainder theorems II (New CRT-II) [6]. This paper presents an alternative architecture derived by Mixed-Radix conversion for this four-moduli set. Due to the using simple multiplicative inverses of the proposed moduli set, it can considerably reduce the complexity of the RNS to binary converter based on the Mixed-Radix conversion. The hardware architecture for the proposed converter is based on the adders and subtractors, without the needed ROM or multipliers.


2021 ◽  
Vol 22 (3) ◽  
Author(s):  
Zeinab Torabi ◽  
Somaye Timarchi

Comparison, division and sign detection are considered complicated operations in residue number system (RNS). A straightforward solution is to convert RNS numbers into binary formats and then perform complicated operations using conventional binary operators. If efficient circuits are provided for comparison, division and sign detection, the application of RNS can be extended to the cases including these operations.For RNS comparison in the 3-moduli set , we have only found one hardware realization. In this paper, an efficient RNS comparator is proposed for the moduli set  which employs sign detection method and operates more efficient than its counterparts. The proposed sign detector and comparator utilize dynamic range partitioning (DRP), which has been recently presented for unsigned RNS comparison. Delay and cost of the proposed comparator are lower than the previous works and makes it appropriate for RNS applications with limited delay and cost.


Author(s):  
Salamudeen Alhassan ◽  
Mohammed Muniru Iddrisu ◽  
Mohammed Ibrahim Daabo

In this paper, we propose an enhanced perceptual video encryption technique to speed-up and secure cipher video transmitted across networks using Residue Number System (RNS). The technique proposes a new reverse converter with smaller dynamic range using the moduli set {2n-1, 2n, 2n+1} that is integrated into our previous work of [2]. After encryption, cipher video is encoded into three residual videos that have smaller pixel values and ideal for transmission across networks. Instead of transmitting the three (3) residual videos, the technique effectively transmits and decodes only two (2) of them back into the original video with same visual quality. Experimental results show that the technique enhances transmission speed and security of cipher video across networks.


The Residue Number System (RNS) based reverse converter can play as main role in Parallel arithmetic operations of Digital Signal Processing (DSP) applications and VLSI technologies. Normally, by the use of carry adders, the reverse conversion design gives high delay and high power consumption. Due to resolve of above problem, the design of reverse converter is proposed by the use of familiar high speed (less propagation delay) Parallel Prefix - Kogge Stone Adder (PP- KSA). This paper describes the design of 32-bit Reverse converter with regular PP-KSA and proposed MUX (Multiplex) logic of PP-KSA with Hybrid Modular Parallel Prefix structure (HMPE) separately. In addition to that, the performance of that designs are analysed based on area, delay and power independently. The Performance results of proposed MUX logic of PP-KSA Reverse converter design yields low power than the other design which uses the regular PP-KSA. The simulation and synthesis effects can be done in Xilinx ISE 14.2i tool.


2017 ◽  
Vol 2 (6) ◽  
pp. 25-30 ◽  
Author(s):  
Alhassan Abdul- Barik ◽  
Mohammed Ibrahim Daabo ◽  
Stephen Akobre

The greatest difficulty of compressing data is the assurance of the security, integrity, and accuracy of the data in storage in volatile media or transmission in network communication channels. Various methods have been proposed for dealing with the accuracy and consistency of compressed and encrypted data using error detection and correction mechanisms. The Redundant Residue Number System (RRNS) which is a trait of Residue Number System (RNS) is one of the available methods for detecting and correcting errors which involves the addition of extra moduli called redundant moduli. In this paper, Residue Number System (RNS) is efficiently applied to the Lempel-Ziv-Welch (LZW) compression algorithm resulting in new LZW-RNS compression scheme using the traditional moduli set, and two redundant moduli added resulting in the moduli set {2^n-1,〖 2〗^n,〖 2〗^n+1,〖 2〗^2n-3,〖 2〗^2n+1} for the purposes of error detection and correction. This is done by constraining the data or information within the legitimate range of the dynamic range provided by the non-redundant moduli. Simulation with MatLab shows the efficiency and fault tolerance of the proposed scheme than the traditional LZW compression method and other related known state of the art schemes.


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