A current-mode successive approximation analog-to-digital conversion technique

Cmos Technology ◽

Digital Systems ◽

Digital Converter ◽

Digital Conversion ◽

Analog To Digital ◽

Analog Signals ◽

Null Convention Logic ◽

The One

In this paper, a novel architecture for self-timed analog-to-digital conversion is presented and designed using the NULL Convention Logic (NCL) paradigm. This analog-to-digital converter (ADC) employs successive approximation and a one-hot encoded masking technique to digitize analog signals. The architecture scales readily to any given resolution by utilizing the one-hot encoded scheme to permit identical logical components for each bit of resolution. The four-bit configuration of the proposed design has been implemented and assessed via simulation in 0.18-μm CMOS technology. Furthermore, the ADC may be interfaced with either synchronous or four-phase asynchronous digital systems.

Successive approximation analog-to-digital conversion at video rates

IEEE Journal of Solid-State Circuits ◽

10.1109/jssc.1981.1051564 ◽

1981 ◽

Vol 16 (3) ◽

pp. 147-151 ◽

Cited By ~ 8

Author(s):

P.H. Saul

Keyword(s):

Digital Conversion ◽

Analog To Digital ◽

Analog To Digital Conversion

A successive approximation analog to digital conversion system with good differential linearity

Nuclear Instruments and Methods in Physics Research ◽

10.1016/0167-5087(82)90151-x ◽

1982 ◽

Vol 199 (3) ◽

pp. 497-503 ◽

Cited By ~ 4

Author(s):

D.E. Carter ◽

G. Randers-Pehrson

Keyword(s):

Digital Conversion ◽

Analog To Digital ◽

Conversion System

A Multi-bit High Speed Current Mode Analog to Digital Conversion Algorithm

IOSR Journal of VLSI and Signal processing ◽

10.9790/4200-0332331 ◽

2013 ◽

Vol 3 (3) ◽

pp. 23-31

Author(s):

Veepsa Bhatia ◽

Keyword(s):

High Speed ◽

Current Mode ◽

Digital Conversion ◽

Analog To Digital ◽

Conversion Algorithm ◽

Analog To Digital Conversion

Systematization and Comparison of the Binary Successive Approximation Variants

Sensors ◽

10.3390/s21248267 ◽

2021 ◽

Vol 21 (24) ◽

pp. 8267

Author(s):

Konrad Jurasz ◽

Dariusz Kościelnik ◽

Jakub Szyduczyński ◽

Marek Miśkowicz

Keyword(s):

Energy Consumption ◽

Direct Conversion ◽

Conversion Process ◽

Digital Converter ◽

Time Intervals ◽

Digital Conversion ◽

Analog To Digital ◽

Physical Quantities

This paper presents a systematization and a comparison of the binary successive approximation (SA) variants. Three different variants are distinguished and all of them are applied in the analog-to-digital conversion. Regardless of an analog-to-digital converter circuit solution, the adoption of the specific SA variant imposes a particular character of the conversion process and related parameters. One of them is the ability to direct conversion of non-removeable physical quantities such as time intervals. Referencing to this aspect a general systematization of the variants and a name for each of them is proposed. In addition, the article raises the issues related to the complexity of implementation and energy consumption for each of the discussed binary SA variants.

BIT ERROR NOTIFICATION AND ESTIMATION IN REDUNDANT SUCCESSIVE-APPROXIMATION ADC

Informatyka Automatyka Pomiary w Gospodarce i Ochronie Środowiska ◽

10.35784/iapgos.2225 ◽

2020 ◽

Vol 10 (4) ◽

pp. 29-32

Author(s):

Serhii Zakharchenko ◽

Roman Humeniuk

Keyword(s):

Transfer Function ◽

Digital Conversion ◽

Analog To Digital ◽

Successive Approximation Adc ◽

Number Systems ◽

Conversion Mode ◽

Redundant Number Systems ◽

The Relationship

The article is devoted to research on the possibilities to use redundant number systems for bit error notification in a successive-approximation ADC during the main conversion mode. The transfer function of a successive-approximation ADC with a non-binary radix is analyzed. If the radix is less than 2, not all possible code combinations appear on the converter output. The process of formation of unused combinations is investigated. The relationship between the bit’s deviations and the list of unused combinations is established. The possibilities of estimating the bit error value without interrupting the process of analog-to-digital conversion is considered.