scholarly journals Systematization and Comparison of the Binary Successive Approximation Variants

Sensors ◽  
2021 ◽  
Vol 21 (24) ◽  
pp. 8267
Author(s):  
Konrad Jurasz ◽  
Dariusz Kościelnik ◽  
Jakub Szyduczyński ◽  
Marek Miśkowicz
Keyword(s):  
Energy Consumption ◽  
Successive Approximation ◽  
Direct Conversion ◽  
Conversion Process ◽  
Digital Converter ◽  
Time Intervals ◽  
Digital Conversion ◽  
Analog To Digital ◽  
Analog To Digital Conversion ◽  
Physical Quantities

This paper presents a systematization and a comparison of the binary successive approximation (SA) variants. Three different variants are distinguished and all of them are applied in the analog-to-digital conversion. Regardless of an analog-to-digital converter circuit solution, the adoption of the specific SA variant imposes a particular character of the conversion process and related parameters. One of them is the ability to direct conversion of non-removeable physical quantities such as time intervals. Referencing to this aspect a general systematization of the variants and a name for each of them is proposed. In addition, the article raises the issues related to the complexity of implementation and energy consumption for each of the discussed binary SA variants. 

SELF-TIMED ARCHITECTURE FOR MASKED SUCCESSIVE APPROXIMATION ANALOG-TO-DIGITAL CONVERSION

2007 ◽  
Vol 16 (01) ◽  
pp. 1-14
Author(s):  
TASKIN KOCAK ◽  
GEORGE R. HARRIS ◽  
RONALD F. DEMARA
Keyword(s):  
Successive Approximation ◽  
Cmos Technology ◽  
Digital Systems ◽  
Digital Converter ◽  
Digital Conversion ◽  
Analog To Digital ◽  
Analog Signals ◽  
Analog To Digital Conversion ◽  
Null Convention Logic ◽  
The One

In this paper, a novel architecture for self-timed analog-to-digital conversion is presented and designed using the NULL Convention Logic (NCL) paradigm. This analog-to-digital converter (ADC) employs successive approximation and a one-hot encoded masking technique to digitize analog signals. The architecture scales readily to any given resolution by utilizing the one-hot encoded scheme to permit identical logical components for each bit of resolution. The four-bit configuration of the proposed design has been implemented and assessed via simulation in 0.18-μm CMOS technology. Furthermore, the ADC may be interfaced with either synchronous or four-phase asynchronous digital systems.

SSDCα – Inherently robust integrated biomimetic sensor-to-spike-to-digital converter based on peripheral neural ensembles

2016 ◽  
Vol 83 (9) ◽  
Author(s):  
Abhaya Chandra Kammara S. ◽  
Andreas König
Keyword(s):  
Digital Converter ◽  
Digital Conversion ◽  
Analog To Digital ◽  
Neural Ensembles ◽  
Analog To Digital Conversion ◽  
Technology Nodes ◽  
Biomimetic Sensor

AbstractRethinking analog to digital conversion has become extremely crucial in the race towards aggressively scaled technology nodes with decaying signal swings. The concept of more recent TDCs, which are completely designed in digital domain, make them simpler, easier to manufacture and faster to market. In previous work, LUCOS

Programmable Nonlinear Adc: An Illustrative Example

1996 ◽  
Vol 33 (3) ◽  
pp. 216-224
Author(s):  
Dinesh K. Anvekar ◽  
B. S. Sonde
Keyword(s):  
Transfer Characteristic ◽  
Analog To Digital Converter ◽  
Analytical Evaluation ◽  
Digital Converter ◽  
Digital Conversion ◽  
Analog To Digital ◽  
Analog To Digital Conversion ◽  
Experimental Implementation ◽  
Nonlinear Analog

Programmable nonlinear ADC: an illustrative example Programmable nonlinear analog-to-digital conversion is a new topic in EE curricula. With a view to introducing the EE student to the concept of transfer characteristic programmability of an analog-to-digital converter (ADC), a memory-prefetch programmable nonlinear ADC is presented. The design, analytical evaluation, and experimental implementation for the ADC are described.

scholarly journals BIT ERROR NOTIFICATION AND ESTIMATION IN REDUNDANT SUCCESSIVE-APPROXIMATION ADC

2020 ◽  
Vol 10 (4) ◽  
pp. 29-32
Author(s):  
Serhii Zakharchenko ◽  
Roman Humeniuk
Keyword(s):  
Transfer Function ◽  
Successive Approximation ◽  
Digital Conversion ◽  
Analog To Digital ◽  
Successive Approximation Adc ◽  
Number Systems ◽  
Conversion Mode ◽  
Analog To Digital Conversion ◽  
Redundant Number Systems ◽  
The Relationship

The article is devoted to research on the possibilities to use redundant number systems for bit error notification in a successive-approximation ADC during the main conversion mode. The transfer function of a successive-approximation ADC with a non-binary radix is analyzed. If the radix is less than 2, not all possible code combinations appear on the converter output. The process of formation of unused combinations is investigated. The relationship between the bit’s deviations and the list of unused combinations is established. The possibilities of estimating the bit error value without interrupting the process of analog-to-digital conversion is considered.

Energy Harvesting via Analog-to-Digital Conversion

2021 ◽  
Author(s):  
Neha Jain ◽  
Nir Shlezinger ◽  
Yonina C. Eldar ◽  
Anubha Gupta ◽  
Vivek Ashok Bohara
Keyword(s):  
Energy Harvesting ◽  
Digital Conversion ◽  
Analog To Digital ◽  
Analog To Digital Conversion

Design of a 20-Gsps 12-bit time-interleaved analog-to-digital conversion system

2021 ◽  
Vol 32 (3) ◽  
Author(s):  
Ruo-Shi Dong ◽  
Lei Zhao ◽  
Jia-Jun Qin ◽  
Wen-Tao Zhong ◽  
Yi-Chun Fan ◽  
...  
Keyword(s):  
Digital Conversion ◽  
Analog To Digital ◽  
Analog To Digital Conversion ◽  
Conversion System ◽  
Time Interleaved
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