scholarly journals A DESIGN FOR VERIFICATION APPROACH USING AN EMBEDDING OF PSL IN AsmL

2007 ◽  
Vol 16 (06) ◽  
pp. 859-881 ◽  
Author(s):  
AMJAD GAWANMEH ◽  
SOFIÈNE TAHAR ◽  
HAJA MOINUDEEN ◽  
ALI HABIBI

In this paper, we propose to integrate an embedding of Property Specification Language (PSL) in Abstract State Machines Language (AsmL) with a top–down design for verification approach in order to enable the model checking of large systems at the early stages of the design process. We provide a complete embedding of PSL in the ASM language AsmL, which allows us to integrate PSL properties as a part of the design. For verification, we propose a technique based on the AsmL tool that translates the code containing both the design and the properties into a finite state machine (FSM) representation. We use the generated FSM to run model checking on an external tool, here SMV. Our approach takes advantage of the AsmL language capabilities to model designs at the system level as well as from the power of the AsmL tool in generating both C# code and FSMs from AsmL models. We applied our approach on the PCI-X bus standard, which AsmL model was constructed from the informal standard specifications and a subsequent UML model. Experimental results on the PCI-X bus case study showed a superiority of our approach to conventional verification.

Author(s):  
Alexander Barkalov ◽  
Larysa Titarenko ◽  
Sławomir Chmielewski

Reduction in the Number of PAL Macrocells in the Circuit of a Moore FSMOptimization methods of logic circuits for Moore finite-state machines are proposed. These methods are based on the existence of pseudoequivalent states of a Moore finite-state machine, a wide fan-in of PAL macrocells and free resources of embedded memory blocks. The methods are oriented to hypothetical VLSI microcircuits based on the CPLD technology and containing PAL macrocells and embedded memory blocks. The conditions of effective application of each proposed method are shown. An algorithm to choose the best model of a finite-state machine for given conditions is proposed. Examples of proposed methods application are given. The effectiveness of the proposed methods is also investigated.


2000 ◽  
Vol 12 (9) ◽  
pp. 2129-2174 ◽  
Author(s):  
Rafael C. Carrasco ◽  
Mikel L. Forcada ◽  
M. Ángeles Valdés-Muñoz ◽  
Ramón P. Ñeco

There has been a lot of interest in the use of discrete-time recurrent neural nets (DTRNN) to learn finite-state tasks, with interesting results regarding the induction of simple finite-state machines from input–output strings. Parallel work has studied the computational power of DTRNN in connection with finite-state computation. This article describes a simple strategy to devise stable encodings of finite-state machines in computationally capable discrete-time recurrent neural architectures with sigmoid units and gives a detailed presentation on how this strategy may be applied to encode a general class of finite-state machines in a variety of commonly used first- and second-order recurrent neural networks. Unlike previous work that either imposed some restrictions to state values or used a detailed analysis based on fixed-point attractors, our approach applies to any positive, bounded, strictly growing, continuous activation function and uses simple bounding criteria based on a study of the conditions under which a proposed encoding scheme guarantees that the DTRNN is actually behaving as a finite-state machine.


2015 ◽  
Vol 24 (07) ◽  
pp. 1550101 ◽  
Author(s):  
Raouf Senhadji-Navaro ◽  
Ignacio Garcia-Vargas

This work is focused on the problem of designing efficient reconfigurable multiplexer banks for RAM-based implementations of reconfigurable state machines. We propose a new architecture (called combination-based reconfigurable multiplexer bank, CRMUX) that use multiplexers simpler than that of the state-of-the-art architecture (called variation-based reconfigurable multiplexer bank, VRMUX). The performance (in terms of speed, area and reconfiguration cost) of both architectures is compared. Experimental results from MCNC finite state machine (FSM) benchmarks show that CRMUX is faster and more area-efficient than VRMUX. The reconfiguration cost of both multiplexer banks is studied using a behavioral model of a reconfigurable state machine. The results show that the reconfiguration cost of CRMUX is lower than that of VRMUX in most cases.


2018 ◽  
Author(s):  
Dihin Muriyatmoko

Finite state machines have becomeextremely popular over the last decade and helpedgame developers build some pretty fun RTS games[1]. Finite State Machines have been widely used asa tool for developing RTS games, especially aspertains to solving problems related to AI, inputhandling, and game progression [2]. Anyhow, tocontrol game play and user interface for SupplyChain Management (SCM) of Food on RTS gameonly played conventional finite state machine(FSM) design. Therefore in this research isdeveloped Food SCM using Hierarchical StateFinite Machine (HFSM).HFSM allow for a modulardevelopment of states that is more maintainable andscalable[3]. The formalism of HFSM makes thestate machine approach truly applicable to real-lifeembedded systems [4].


1984 ◽  
Vol 28 (6) ◽  
pp. 510-510
Author(s):  
Virginia A. Rappold ◽  
John L. Sibert

The purpose of this case study was to document and evaluate the application of a top-down design methodology (Foley & van Dam, 1982) to a pre-existing computer system to test the methodology's usefulness as well as to gain insights into the design process itself. System experts advocate design of a system “top-down” instead of “bottom-up” as a way to sequentially examine the complex task of interface design while allowing re-examination of previous steps in that design (Foley, 1981). The study involved a menu-based, mini-computer system designed at Goddard Space Flight Center called the Mission Planning Terminal (MPT). The MPT will be used at Goddard for planning and scheduling of satellite activities through the NASA Network Control Center (NCC). The scheduler/analyst's task includes submitting a schedule of activities for his mission, transmitting it to NCC, and then modifying the returned schedule, if necessary, using the MPT. The top-down design process is distinctly divided into four phases: conceptual, semantic, syntactic, and lexical (Foley, 1981). The first phase, conceptual, consists of defining key application concepts needed by the user. The semantic phases involve defining meanings such as information needed in order to use an object. The syntactic design defines sequences of inputs (similar to English grammar rules) and outputs (the two and three dimensional organization of the display). The last step, lexical design, describes how words in the input/output sequence are formed from the existing hardware input (Foley & van Dam, 1982). The top-down methodology was applied using MPT documentation and interviews with the designers. During this process, it became clear that although a conceptual model of the MPT existed somewhere, it was never recorded. This led to numerous attempts to extract the main conceptual components of the system from the software operations documents which were constantly changed and were often incomplete. Finally, based on preliminary screen designs, state diagrams were constructed to map out components of the system. By characterization of the MPT in this way (using state diagrams), a clearer picture emerged that finally led to understanding the conceptual model. Once the conceptual model was extracted, redesign of the system, using the top-down method, quickly followed. This case study clearly emphasizes the need for a complete and accurate conceptual model if a top-down approach is to be applied. When redesigning an existing system, it frequently becomes necessary to “extract” this model in a bottom-up manner as was the case here.


2020 ◽  
Vol 64 (7) ◽  
pp. 1445-1481
Author(s):  
Gabriele Costa ◽  
Letterio Galletta ◽  
Pierpaolo Degano ◽  
David Basin ◽  
Chiara Bodei

Abstract Verifying the correctness of a system as a whole requires establishing that it satisfies a global specification. When it does not, it would be helpful to determine which modules are incorrect. As a consequence, specification decomposition is a relevant problem from both a theoretical and practical point of view. Until now, specification decomposition has been independently addressed by the control theory and verification communities through natural projection and partial model checking, respectively. We prove that natural projection reduces to partial model checking and, when cast in a common setting, the two are equivalent. Apart from their foundational interest, our results build a bridge whereby the control theory community can reuse algorithms and results developed by the verification community. Furthermore, we extend the notions of natural projection and partial model checking from finite-state to symbolic transition systems and we show that the equivalence still holds. Symbolic transition systems are more expressive than traditional finite-state transition systems, as they can model large systems, whose behavior depends on the data handled, and not only on the control flow. Finally, we present an algorithm for the partial model checking of both kinds of systems that can be used as an alternative to natural projection.


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