A Body Bias Generator with Low Supply Voltage for Within-Die Variability Compensation

2014 ◽  
Vol E97.A (3) ◽  
pp. 734-740 ◽  
Author(s):  
Norihiro KAMAE ◽  
Akira TSUCHIYA ◽  
Hidetoshi ONODERA
Keyword(s):  
Supply Voltage ◽  
Variability Compensation ◽  
Low Supply Voltage ◽  
Body Bias

COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS

2014 ◽  
Vol 23 (08) ◽  
pp. 1450108 ◽  
Author(s):  
VANDANA NIRANJAN ◽  
ASHWANI KUMAR ◽  
SHAIL BALA JAIN
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Signal Frequency ◽  
Output Impedance ◽  
Self Cascode ◽  
Intrinsic Gain ◽  
Body Bias

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

LOOKUP TABLE-BASED ADAPTIVE BODY BIASING OF MULTIPLE MACROS FOR PROCESS VARIATION COMPENSATION AND LOW LEAKAGE

2010 ◽  
Vol 19 (07) ◽  
pp. 1449-1464 ◽  
Author(s):  
BYUNGHEE CHOI ◽  
YOUNGSOO SHIN
Keyword(s):  
Supply Voltage ◽  
Process Variation ◽  
Power Saving ◽  
Lookup Table ◽  
Low Leakage ◽  
Fine Grain ◽  
Body Biasing ◽  
Block Level ◽  
Adaptive Body Bias ◽  
Body Bias

A reduced supply voltage must be accompanied by a reduced threshold voltage, which makes this approach to power saving susceptible to process variation in transistor parameters, as well as resulting in increased subthreshold leakage. While adaptive body biasing is efficient for both compensating process variation and suppressing leakage current, it suffers from a large overhead of control circuit. Most body biasing circuits target an entire chip, which causes excessive leakage of some blocks and misses the chance of fine grain control. We propose a new adaptive body biasing scheme, based on a lookup table for independent control of multiple functional blocks on a chip, which controls leakage and also compensates for process variation at the block level. An adaptive body bias is applied to blocks in active mode and a large reverse body bias is applied to blocks in standby mode. This is achieved by a central body bias controller, which has a low overhead in terms of area, delay, and power consumption. The problem of optimizing the required set of bias voltages is formulated and solved. A design methodology for semicustom design using standard-cell elements is developed and verified with benchmark circuits.

A new erasing and row decoding scheme for low supply voltage operation 16-Mb/64-Mb flash memories

1992 ◽  
Vol 27 (4) ◽  
pp. 583-588 ◽  
Author(s):  
Y. Miyawaki ◽  
T. Nakayama ◽  
S. Kobayashi ◽  
N. Ajika ◽  
M. Ohi ◽  
...  
Keyword(s):  
Supply Voltage ◽  
Flash Memories ◽  
Low Supply Voltage

A 12-BIT 400-MS/s CURRENT-STEERING DAC WITH DEGLITCHING TECHNIQUE

2014 ◽  
Vol 23 (01) ◽  
pp. 1450004 ◽  
Author(s):  
XIAOBO XUE ◽  
XIAOLEI ZHU ◽  
QIFENG SHI ◽  
LENIAN HE
Keyword(s):  
Dynamic Range ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Signal Frequency ◽  
Current Steering ◽  
Digital To Analog Converter ◽  
Measurement Results ◽  
Voltage Swing ◽  
Current Steering Dac ◽  
Low Supply Voltage

In this paper, a 12-bit current-steering digital-to-analog converter (DAC) employing a deglitching technique is proposed. The deglitching technique is realized by lowering the voltage swing of the control signal as well as by using a method of glitch counteraction (GC). A new switch–driver structure is designed to enable the effectiveness of the GC and provide sufficient driving capability under a low supply voltage. Moreover, the control signal's rise/fall asymmetry which increases the glitch error can be suppressed by using the proposed switch–driver structure. The 12-bit DAC is implemented in 180 nm CMOS technology. The measurement results show that the spurious free dynamic range (SFDR) at low signal frequency is 78.8 dB, and it is higher than 70 dB up to 60 MHz signal frequency at 400 MS/s. The measured INL and DNL are both less than ±0.6 LSB.

A simple circuit for driving light-emitting diodes with low supply voltage

2000 ◽  
Vol 71 (3) ◽  
pp. 1569-1570 ◽  
Author(s):  
Tai-Shan Liao ◽  
Chun-Ming Chang
Keyword(s):  
Light Emitting Diodes ◽  
Supply Voltage ◽  
Simple Circuit ◽  
Light Emitting ◽  
Low Supply Voltage

scholarly journals DVCC-based Low-power RF Filter with 32 nm CNFETs

2021 ◽  
Author(s):  
Shailendra Tripathi ◽  
Amit Mahesh Joshi
Keyword(s):  
Low Power ◽  
Analog Circuits ◽  
Satellite Communication ◽  
Supply Voltage ◽  
Wide Band ◽  
Rf Receiver ◽  
Rf Filter ◽  
Low Supply Voltage ◽  
Differential Voltage Current Conveyor ◽  
Carbon Nanotube Fet

Abstract This work presents a wide-band active filter for RF receiver. The design uses Carbon Nanotube-FET (CNFET) based differential voltage current conveyor (DVCC) for the implementation of the proposed filter. The filter is designed to operate Ku-band frequencies (12-18 GHz), which is used in satellite communication. Additionally, CMOS based circuit and CNFET-based circuit for DVCC are compared for the performance evaluation. HSPICE simulations have been carried out to test the design aspects of the circuit. The CNFET-based circuit has better results in terms of 60 % reduction in the power consumption and about six times improvement in the bandwidth. The filter utilizes low supply voltage of 0.9 V and consumes 524 µW only. The proposed filter outperforms the existing CMOS-based designs which suggests its usage for low-power high-frequency analog circuits.

Sign in / Sign up

Export Citation Format

Share Document