LOW VOLTAGE CURRENT CONVEYOR-BASED FIELD PROGRAMMABLE ANALOG ARRAY

2011 ◽  
Vol 20 (08) ◽  
pp. 1677-1701 ◽  
Author(s):  
SOLIMAN A. MAHMOUD ◽  
EMAN A. SOLIMAN
Keyword(s):  
Low Voltage ◽  
Second Order ◽  
Current Conveyor ◽  
Total Power ◽  
Band Pass Filter ◽  
Pass Filter ◽  
Programmable Analog ◽  
Total Power Consumption ◽  
Field Programmable ◽  
Field Programmable Analog Array

In this paper a low voltage low power field programmable analog array (FPAA) is realized. The FPAA configurable analog block (CAB) design is based on three-bit digitally controlled fully differential current conveyor. The FPAA consists of seven CABs. The CABs are directly connected together without adding extra hardware by placing them in a hexagonal lattice arrangement. A variable gain amplifier, tunable second-order low-pass filter, and a tunable second-order band-pass filter are realized as an application for the FPAA. The FPAA total power consumption is 105.12 mW at 1 V supply. The FPAA is realized using IBM 90 nm CMOS technology model from MOSIS under voltage supply of ±0.5 V.

DESIGN OF COMPLEX BAND-PASS FILTERS BASED ON PROGRAMMABLE ANALOG INTEGRATED CIRCUITS

2020 ◽  
Author(s):  
Ю.А. ГРЕБЕНКО ◽  
КО.М. АУНГ
Keyword(s):  
Integrated Circuits ◽  
Band Pass Filter ◽  
Third Order ◽  
Pass Filter ◽  
Method Of Calculation ◽  
Programmable Analog ◽  
Field Programmable ◽  
Band Pass ◽  
Order Butterworth Filter ◽  
Field Programmable Analog Array

Приведена методика расчета и реализации комплексного полосового фильтра с заданными координатами полюсов НЧ-прототипа на базе ПАИС фирмы Anadigm. Моделирование проводилось с помощью САПР AnadigmDesigner2. Описан пример реализации на ПАИС комплексного полосового фильтра Баттерворта 3-го порядка. This article describes the method of calculation and implementation of a complex band-pass filter with the specified coordinates of the poles of the LF-prototypes based on field programmable analog array (FPAA) of company Anadigm. Modeling was carried on with the help of CAD AnadigmDesigner2. An example of implementing a complex third-order Butterworth filter on FPAA is described.

scholarly journals Noise-Cancelling CMOS Active Inductor and Its Application in RF Band-Pass Filter Design

2010 ◽  
Vol 2010 ◽  
pp. 1-8 ◽  
Author(s):  
Santosh Vema Krishnamurthy ◽  
Kamal El-Sankary ◽  
Ezz El-Masry
Keyword(s):  
Filter Design ◽  
Low Noise ◽  
Total Power ◽  
Active Inductor ◽  
Cmos Process ◽  
Band Pass Filter ◽  
Pass Filter ◽  
Noise Cancelling ◽  
Total Power Consumption ◽  
Band Pass

A CMOS active inductor with thermal noise cancelling is proposed. The noise of the transistor in the feed-forward stage of the proposed architecture is cancelled by using a feedback stage with a degeneration resistor to reduce the noise contribution to the input. Simulation results using 90 nm CMOS process show that noise reduction by 80% has been achieved. The maximum resonant frequency and the quality factor obtained are 3.8 GHz and 405, respectively. An RF band-pass filter has been designed based on the proposed noise cancelling active inductor. Tuned at 3.46 GHz, the filter features total power consumption of 1.4 mW, low noise figure of 5 dB, and IIP3 of −10.29 dBm.

IMPLEMENTATION ISSUES FOR HIGH-BANDWIDTH FIELD-PROGRAMMABLE ANALOG ARRAYS

1998 ◽  
Vol 08 (05n06) ◽  
pp. 541-558 ◽  
Author(s):  
VINCENT C. GAUDET ◽  
P. GLENN GULAK
Keyword(s):  
Cmos Technology ◽  
Current Conveyor ◽  
Test Results ◽  
Programmable Analog ◽  
Field Programmable ◽  
High Bandwidth ◽  
Field Programmable Analog Arrays ◽  
Analog Arrays ◽  
A Current ◽  
Field Programmable Analog Array

This paper is a tutorial introduction to field-programmable analog arrays, as well as a review of existing field-programmable analog array architectures, of both educational and industrial origin. Circuit issues relevant to the development of high-bandwidth FPAAs are presented. A current conveyor-based architecture, which promises to achieve video bandwidths, is described. Test results are presented for the CMOS current conveyor-based FPAA building block, with programmable transconductors and capacitors. Measurements indicate bandwidths in excess of 10 MHz, and functionality of amplifiers, integrators, differentiators, and adders. The die area is 1.5 mm× 3.5 mm in a 0.8 μm CMOS technology.

LOW-POWER, LOW-VOLTAGE, DUAL-OUTPUT, SECOND GENERATION CURRENT CONVEYOR AND ITS APPLICATION IN LOW-PASS FILTER DESIGN

2013 ◽  
Vol 22 (06) ◽  
pp. 1350044 ◽  
Author(s):  
MOHAMMAD HOSSEIN MAGHAMI ◽  
AMIR M. SODAGAR
Keyword(s):  
Second Generation ◽  
Current Conveyor ◽  
The Body ◽  
Total Power ◽  
Cmos Process ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Silicon Area ◽  
Total Power Consumption ◽  
Low Pass

A new simple dual-output second generation current conveyor (DO-CCII) circuit is proposed. Designed in a standard 0.5-μm CMOS process, the circuit operates at ±1.5 V supply voltages with a total power consumption of 106 nW. Main characteristics of the proposed DO-CCII are its simplicity, small silicon area consumption, and not suffering from the body effect of MOS transistors. The proposed circuit is employed to implement a first-order low-pass filter with upper -3 dB cut-off frequency of as low as 3.2 Hz.

Extremum Seeking Based Control Strategy for a Chilled-Water Plant With Parallel Chillers

2015 ◽  
Author(s):  
Baojie Mu ◽  
Yaoyu Li ◽  
Timothy I. Salsbury ◽  
John M. House
Keyword(s):  
Control Strategy ◽  
Cooling Tower ◽  
Input Saturation ◽  
Extremum Seeking ◽  
Total Power ◽  
Band Pass Filter ◽  
Pass Filter ◽  
Water Plant ◽  
Total Power Consumption ◽  
Chilled Water

Chilled-water plants with multiple chillers are the backbone of ventilation and air conditioning (VAC) systems for commercial buildings. A penalty function based multivariate extremum seeking control (ESC) strategy is proposed in this paper for maximizing the energy efficiency in real time for a variable primary flow (VPF) chilled-water plant with parallel chillers. The proposed ESC algorithm takes the total power consumption (chiller compressors + cooling tower fan + condenser water pumps + penalty terms if inputs saturation occurs) as feedback, and tower fan air flow, condenser water flows and evaporator leaving chilled-water temperature setpoint as plant inputs (ESC outputs). A band-pass filter array is used in place of the conventional high-pass filter at the plant output so as to reduce the cross-channel interference. Chiller sequencing is also enabled with input saturation related signals. A Modelica based dynamic simulation model is developed for a chilled-water plant with two parallel chillers, one cooling tower, one air-handling unit and one zone. Simulation results under several testing conditions validate the effectiveness of the proposed model-free control strategy, as well as the significant energy saving.

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