MASH DDSM with Negative Feedback

This paper proposes a Multi-stAge noise SHaping (MASH) digital delta-sigma modulator (DDSM) with negative feedback to acquire the maximum sequence length. The mathematical analysis shows that the sequence length is [Formula: see text], which is not affected by the input values and initial conditions, where [Formula: see text] is the smallest prime number above the quantization interval [Formula: see text], and [Formula: see text] is the order of the MASH DDSM. Moreover, the influence of the negative feedback on the input range is analyzed. Finally, the simulations and experiments are performed to verify the theoretical analysis.

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Digital Mobile Fronthaul Based on Performance Enhanced Multi-Stage Noise-Shaping Delta-Sigma Modulator

Journal of Lightwave Technology ◽

10.1109/jlt.2020.3027911 ◽

2021 ◽

Vol 39 (2) ◽

pp. 439-447

Author(s):

Ke Bai ◽

Dongdong Zou ◽

Zixuan Zhang ◽

Zibin Li ◽

Wei Wang ◽

...

Keyword(s):

Noise Shaping ◽

Delta Sigma Modulator ◽

Multi Stage ◽

Delta Sigma

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The Delta-Sigma Modulator of Fractional-N Frequency Synthesizer for Wireless Sensors Network Applications

Key Engineering Materials ◽

10.4028/www.scientific.net/kem.609-610.1014 ◽

2014 ◽

Vol 609-610 ◽

pp. 1014-1019 ◽

Cited By ~ 1

Author(s):

Zhi Qiang Gao ◽

Jin Bao Lan ◽

Xiao Wei Liu ◽

Liang Yin

Keyword(s):

Frequency Synthesizer ◽

Linear Feedback ◽

Cmos Process ◽

Noise Shaping ◽

Network Applications ◽

Delta Sigma Modulator ◽

Multi Stage ◽

Delta Sigma ◽

Third Stage ◽

Feedback Shift Register

This paper presents a design of fractional-N frequency synthesizer with low dithering, which is fabricated in a 130nm CMOS process. A 3rd-order delta-sigma modulator is based on digital multi-stage noise shaping (MASH) structure with its second and third stage dithered by 7-bit linear feedback shift register (LFSR) was designed for the frequency synthesizer, and a long word is used for the first modulator in the MASH structure. The simulation result of the whole frequency synthesizer shows that it can output two-way I/Q signal between 2.28GHz and 2.53GHz, and its spurs are lower than-75dBc.

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A Novel Architecture of Pseudorandom Dithered MASH Digital Delta-Sigma Modulator with Lower Spur

Journal of Circuits System and Computers ◽

10.1142/s0218126616500729 ◽

2016 ◽

Vol 25 (07) ◽

pp. 1650072

Author(s):

Seyed Ali Sadat Noori ◽

Ebrahim Frashidi ◽

Sirus Sadughi

Keyword(s):

Quantization Noise ◽

Noise Shaping ◽

Constant Input ◽

Finite Precision ◽

Delta Sigma Modulator ◽

Multi Stage ◽

Delta Sigma ◽

Spurious Tones ◽

Finite State ◽

Novel Method

A Digital Delta Sigma Modulator (DDSM) is a Finite State Machine (FSM); it is implemented using finite precision arithmetic units and the number of available states is finite. The DDSM always produces a periodic output signal when the input is constant. This paper proposes a novel method of applying periodic dither to a DDSM in order to obtain minimized spurious tones. The effects of adding the pseudorandom dither signal in different stages within the proposed Multi-Stage noise Shaping (MASH) modulator are expressed in the equations, and the results are compared. We present results regarding the periodicity of the quantization noise produced by a MASH modulator with a constant input and a pseudorandom dither signal. The performance is confirmed mathematically, and by simulation.

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2‐1 Switched‐current multi‐stage noise‐shaping delta–sigma modulator with a digital noise‐cancellation circuit

IET Circuits Devices & Systems ◽

10.1049/iet-cds.2018.5025 ◽

2019 ◽

Vol 13 (3) ◽

pp. 327-336 ◽

Cited By ~ 2

Author(s):

Leenendra Chowdary Gunnam ◽

Guo‐Ming Sung ◽

Lei‐Wen Weng ◽

Te‐Chia Fan

Keyword(s):

Noise Cancellation ◽

Noise Shaping ◽

Delta Sigma Modulator ◽

Multi Stage ◽

Delta Sigma ◽

Switched Current

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A Low-Power Opamp-Less Second-Order Delta-Sigma Modulator for Bioelectrical Signals in 0.18 µm CMOS

Sensors ◽

10.3390/s21196456 ◽

2021 ◽

Vol 21 (19) ◽

pp. 6456

Author(s):

Fernando Cardes ◽

Nikhita Baladari ◽

Jihyun Lee ◽

Andreas Hierlemann

Keyword(s):

Low Power ◽

Low Frequency ◽

Cmos Technology ◽

Low Noise ◽

Second Order ◽

Frequency Noise ◽

Voltage Controlled Oscillator ◽

Noise Shaping ◽

Delta Sigma Modulator ◽

Delta Sigma

This article reports on a compact and low-power CMOS readout circuit for bioelectrical signals based on a second-order delta-sigma modulator. The converter uses a voltage-controlled, oscillator-based quantizer, achieving second-order noise shaping with a single opamp-less integrator and minimal analog circuitry. A prototype has been implemented using 0.18 μm CMOS technology and includes two different variants of the same modulator topology. The main modulator has been optimized for low-noise, neural-action-potential detection in the 300 Hz–6 kHz band, with an input-referred noise of 5.0 μVrms, and occupies an area of 0.0045 mm2. An alternative configuration features a larger input stage to reduce low-frequency noise, achieving 8.7 μVrms in the 1 Hz–10 kHz band, and occupies an area of 0.006 mm2. The modulator is powered at 1.8 V with an estimated power consumption of 3.5 μW.

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