Reversible Circuits Synthesis from Functional Decision Diagrams by using Node Dependency Matrices

2019 ◽  
Vol 29 (05) ◽  
pp. 2050079
Author(s):  
Suzana Stojković ◽  
Radomir Stanković ◽  
Claudio Moraga ◽  
Milena Stanković
Keyword(s):  
Data Structure ◽  
Optimal Order ◽  
Decision Diagrams ◽  
Circuit Synthesis ◽  
Quantum Cost ◽  
Dependency Matrix ◽  
Bottom Level ◽  
Reversible Circuits ◽  
Reversible Circuit ◽  
Toffoli Gates

Decision diagrams are a data structure suitable for reversible circuit synthesis. Functional decision diagrams (FDDs) are particularly convenient in synthesis with Toffoli gates, since the functional expressions for decomposition rules used in them are similar to the functional expressions of Toffoli gates. The main drawback of reversible circuit synthesis based on decision diagrams is the usually large number of ancilla lines. This paper presents two methods for the reduction of the number of ancilla lines in reversible circuits derived from FDDs by selecting the order of implementation of nodes. In the first method, nodes are implemented by levels, starting from the bottom level to the top. The method uses appropriately defined level dependency matrices for choosing the optimal order of implementation of nodes at the same level. In this way, the optimization is performed level by level. The second method uses a diagram dependency matrix expressing mutual dependencies among all the nodes in the diagram. This method is computationally more demanding than the first method, but the reductions of both the number of lines and the Quantum cost of the circuits are larger.

scholarly journals Synthesis of reversible circuits for large reversible functions

2010 ◽  
Vol 23 (3) ◽  
pp. 273-286 ◽  
Author(s):  
Nouraddin Alhagi ◽  
Maher Hawash ◽  
Marek Perkowski
Keyword(s):  
Data Structure ◽  
Real Time ◽  
Large Scale ◽  
Optimal Solution ◽  
Truth Table ◽  
Synthesis Process ◽  
Quantum Cost ◽  
Reversible Circuits ◽  
Gate Count ◽  
Reversible Circuit

This paper presents a new algorithm MP (multiple pass) to synthesize large reversible binary circuits without ancilla bits. The well-known MMD algorithm for synthesis of reversible circuits requires to store a truth table (or a Reed-Muller - RM transform) as a 2n vector to represent a reversible function of n variables. This representation prohibits synthesis of large functions. However, in MP we do not store such an exponentially growing data structure. The values of minterms are calculated in MP dynamically, one-by-one, from a set of logic equations that specify the reversible circuit to be designed. This allows for synthesis of large scale reversible circuits (30-bits), which is not possible with any existing algorithm. In addition, our unique multi-pass approach where the circuit is synthesized with various, yet specific, minterm orders yields quasi-optimal solution. The algorithm returns a description of the quasi-optimal circuit with respect to gate count or to its 'quantum cost'. Although the synthesis process in MP is relatively slower, the solution is found in real-time for smaller circuits of 8 bits or less.

An Efficient Design for Testability Approach of Reversible Logic Circuits

2020 ◽  
pp. 2150094
Author(s):  
Joyati Mondal ◽  
Arighna Deb ◽  
Debesh K. Das
Keyword(s):  
Fault Detection ◽  
Low Power Design ◽  
Design For Testability ◽  
Control Input ◽  
Quantum Cost ◽  
Efficient Design ◽  
Additional Line ◽  
Reversible Circuits ◽  
Reversible Circuit ◽  
Additional Input

Reversible circuits have been extensively investigated because of their applications in areas of quantum computing or low-power design. A reversible circuit is composed of only reversible gates and allow computations from primary inputs to primary outputs and vice-versa. In the last decades, synthesis of reversible circuits received significant interest. Additionally, testing of these kinds of circuits has been studied which included different fault models and test approaches dedicated for reversible circuits only. The analysis of testability issues in a reversible circuit commonly involves the detection of the missing gate faults that may occur during the physical realizations of the reversible gates. In this paper, we propose a design for testability (DFT) technique for reversible circuits in which the gates of a circuit are clustered into different sets and the gates from each cluster are then connected to an additional input line where, the additional line acts as an extra control input to the corresponding gate. Such arrangement makes it possible to achieve [Formula: see text] fault detection in any reversible circuit with a small increase in quantum cost. Experimental evaluations confirm that the proposed DFT technique incurs less quantum cost overhead with [Formula: see text] fault detection compared to existing DFT techniques for reversible circuits.

TIGHT BOUNDS ON THE SYNTHESIS OF 3-BIT REVERSIBLE CIRCUITS: NFFr LIBRARY

2014 ◽  
Vol 23 (03) ◽  
pp. 1450040 ◽  
Author(s):  
AHMED YOUNES
Keyword(s):  
Lower Bound ◽  
Permutation Group ◽  
Minimum Cost ◽  
Synthesis Problem ◽  
Minimum Length ◽  
Circuit Synthesis ◽  
Generating Set ◽  
Reversible Circuits ◽  
Reversible Circuit ◽  
The Cost

The reversible circuit synthesis problem can be reduced to permutation group. This allows Schreier–Sims algorithm for the strong generating set-finding problem to be used to find tight bounds on the synthesis of 3-bit reversible circuits using the NFFr library. The tight bounds include the maximum and minimum length of 3-bit reversible circuits, the maximum and minimum cost of 3-bit reversible circuits. The analysis shows better results than that found in the literature for the lower bound of the cost. The analysis also shows that there are 2460 universal reversible sub-libraries from the main NFFr library.

Novel Synthesis Methodology for Fault Tolerant Reversible Circuits by Bounded Model Checking for Linear Temporal Logic

2015 ◽  
Vol 24 (06) ◽  
pp. 1550091 ◽  
Author(s):  
Ming-Cui Li ◽  
Ri-Gui Zhou
Keyword(s):  
Model Checking ◽  
Temporal Logic ◽  
Fault Tolerant ◽  
Linear Temporal Logic ◽  
Bounded Model Checking ◽  
Quantum Cost ◽  
Step Method ◽  
Synthesis Time ◽  
Reversible Circuits ◽  
Reversible Circuit

Reversible circuit is of interest due to the characteristics of low energy consumption. This paper proposes a new scheme for synthesizing fault tolerant reversible circuits. A two-step method is put forward to convert an irreversible function into a parity-preserving reversible circuit. By introducing model checking for linear temporal logic, we construct a finite state machine to synthesize small reversible gates from elementary 1-qubit and 2-qubit gates, which is more automatic than the methods proposed previously. Constrains are increased so as to reduce the synthesis time in the two step method. The parity-preserving gate constructed by the two-step method has characteristics of low quantum cost because the quantum representation obtained from the counterexample for a given function in each step has the minimum quantum cost. In order to further reduce the quantum cost and decrease the synthesis time, the semi parity-preserving gates are put forward for the first time. These gates are parity-preserving when the auxiliary input is set to 0 and opposite parity when 1. Maintaining good robustness of the system in performing specific function, semi parity-preserving gate is conducive to detecting the stuck-at fault and partial gate fault in reversible circuits. The innovation of this paper is introducing the formal method to synthesis small fault tolerant gate, so as to construct the circuit with robust (semi) parity-preserving gates.

scholarly journals Reversible Circuit Synthesis Time Reduction Based on Subtree-Circuit Mapping

2020 ◽  
Vol 10 (12) ◽  
pp. 4147
Author(s):  
Amjad Hawash ◽  
Ahmed Awad ◽  
Baker Abdalhaq
Keyword(s):  
Large Scale ◽  
Experimental Tests ◽  
Synthesis Process ◽  
Circuit Synthesis ◽  
Quantum Cost ◽  
Synthesis Time ◽  
Reversible Circuit ◽  
Mapping Process ◽  
Time Reduction ◽  
Hash Key

Several works have been conducted regarding the reduction of the energy consumption in electrical circuits. Reversible circuit synthesis is considered to be one of the major efforts at reducing the amount of power consumption. The field of reversible circuit synthesis uses a large number of proposed algorithms to minimize the overall cost of circuits synthesis (represented in the line number and quantum cost), with minimal concern paid for synthesis time. However, because of the iterative nature of the synthesis optimization algorithms, synthesis time cannot be neglected as a parameter which needs to be tackled, especially for large-scale circuits which need to be realized by cascades of reversible gates. Reducing the synthesis cost can be achieved by Binary Decision Diagrams (BDDs), which are considered to be a step forward in this field. Nevertheless, the mapping of each BDD node into a cascade of reversible gates during the synthesis process is time-consuming. In this work, we implement the idea of the subtree-based mapping of BDD nodes to reversible gates instead of the classical nodal-based algorithm to effectively reduce the entire reversible circuit synthesis time. Considering Depth-First Search (DFS), we convert an entire BDD subtree in one step into a cascade of reversible gates. A look-up table for all possible combinations of subtrees and their corresponding reversible gates has been constructed, in which a hash key is used to directly access subtrees during the mapping process. This table is constructed as a result of a comprehensive study of all possible BDD subtrees and considered as a reference during the conversion process. The conducted experimental tests show a significant synthesis time reduction (around 95% on average), preserving the correctness of the algorithm in generating a circuit realizing the required Boolean function.

scholarly journals A reversible circuit synthesis algorithm with progressive increase of controls in generalized Toffoli gates

2021 ◽  
Vol 27 (6) ◽  
pp. 544-563
Author(s):  
Edinelço Dalcumune ◽  
Luis Antonio Brasil Kowada ◽  
André da Cunha Ribeiro ◽  
Celina Miraglia Herrera de Figueiredo ◽  
Franklin de Lima Marquezino
Keyword(s):  
Low Cost ◽  
Progressive Increase ◽  
Experimental Results ◽  
Circuit Synthesis ◽  
Synthesis Algorithm ◽  
Disjoint Cycles ◽  
Gate Count ◽  
Reversible Circuit ◽  
Toffoli Gates ◽  
Negative Controls

We present a new algorithm for synthesis of reversible circuits for arbitrary n-bit bijective functions. This algorithm uses generalized Toffoli gates, which include positive and negative controls. Our algorithm is divided into two parts. First, we use partially controlled gen- eralized Toffoli gates, progressively increasing the number of controls. Second, exploring the properties of the representation of permutations in disjoint cycles, we apply generalized Toffoli gates with controls on all lines except for the target line. Therefore, new in the method is the fact that the obtained circuits use first low cost gates and consider increasing costs towards the end of the synthesis. In addition, we employ two bidirectional synthesis strategies to improve the gate count, which is the metric used to compare the results obtained by our algorithm with the results presented in the literature. Accordingly, our experimental results consider all 3-bit bijective functions and twenty widely used benchmark functions. The results obtained by our synthesis algorithm are competitive when compared with the best results known in the literature, considering as a complexity metric just the number of gates, as done by alternative best heuristics found in the literature. For example, for all 3-bit bijective functions using generalized Toffoli gates library, we obtained the best so far average count of 5.23.

scholarly journals DenseZDD: A Compact and Fast Index for Families of Sets

Algorithms ◽  
2018 ◽  
Vol 11 (8) ◽  
pp. 128 ◽  
Author(s):  
Shuhei Denzumi ◽  
Jun Kawahara ◽  
Koji Tsuda ◽  
Hiroki Arimura ◽  
Shin-ichi Minato ◽  
...  
Keyword(s):  
Data Structure ◽  
Data Structures ◽  
Information Integration ◽  
Decision Diagrams ◽  
Web Information Retrieval ◽  
Binary Decision ◽  
Web Information ◽  
Set Operations ◽  
Succinct Data Structure ◽  
The Family

In this article, we propose a succinct data structure of zero-suppressed binary decision diagrams (ZDDs). A ZDD represents sets of combinations efficiently and we can perform various set operations on the ZDD without explicitly extracting combinations. Thanks to these features, ZDDs have been applied to web information retrieval, information integration, and data mining. However, to support rich manipulation of sets of combinations and update ZDDs in the future, ZDDs need too much space, which means that there is still room to be compressed. The paper introduces a new succinct data structure, called DenseZDD, for further compressing a ZDD when we do not need to conduct set operations on the ZDD but want to examine whether a given set is included in the family represented by the ZDD, and count the number of elements in the family. We also propose a hybrid method, which combines DenseZDDs with ordinary ZDDs. By numerical experiments, we show that the sizes of our data structures are three times smaller than those of ordinary ZDDs, and membership operations and random sampling on DenseZDDs are about ten times and three times faster than those on ordinary ZDDs for some datasets, respectively.

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