Power Estimation and Validation of Embedded Multiplier Based on ANN and Regression Technique

2021 ◽  
Author(s):  
Neerja Singh ◽  
Gaurav Verma ◽  
Vijay Khare
Keyword(s):  
Curve Fitting ◽  
High Performance ◽  
Timing Analysis ◽  
Digital Signal ◽  
Power Estimation ◽  
Critical Issue ◽  
Regression Technique ◽  
Design Stage ◽  
Early Design Stage ◽  
Post Synthesis

Nowadays, high-end Field-Programmable Gate Arrays (FPGAs) are capable of implementing relatively high-performance systems in the field of Digital Signal Processing (DSP). Due to the abundant application of multipliers, their implementation efficiency and performance have become a critical issue in designing the DSP systems. On the other hand, FPGAs consume a large amount of power due to their complex circuitry. So, the power estimation of FPGA implementations at an early design stage has become a critical design metric. Various models are available in the literature based on Look-up Tables (LUTs), but not much literature is available on speed-optimized multiplier design using DSP slices only. In this paper, an embedded multiplier (12.0 IP core) has been analyzed and customized for different Input/Output (I/O) configurations to estimate the power using Vivado Design Suite (2014.4) targeted to the Zynq-family FPGA device (Zynq evolution and development kit). The embedded multiplier IP has been optimized for performance using two different approaches, i.e., Mults (DSP)-based and LUTs-based. Post-synthesis attributes have been used for formulating the power estimation models based on Artificial Neural Network (ANN) and curve fitting and regression technique. The power values estimated from the proposed models have been authenticated with reference to those assessed from the commercial tool. Based on the results obtained, ANN-based model provides average errors of 0.73% and 0.88% for the LUTs and DSP-based designs, respectively. Whereas, the model based on curve fitting and regression technique provides average errors of 3.61% and 1.59% for the LUTs and DSP-based designs, respectively. The timing analysis has been done to get the design performance and time complexity of the proposed models. Area analysis of the design has also been performed in order to report the resource utilization.

A Performance Modeling Language for Automotive Embedded Control Systems Based on UML

2012 ◽  
Vol 236-237 ◽  
pp. 344-349
Author(s):  
Xiao Feng Yin ◽  
Jing Xing Tan ◽  
Xiu Ting Wu ◽  
Zhi Jun Gong
Keyword(s):  
Performance Modeling ◽  
Resource Constraints ◽  
Timing Analysis ◽  
Unified Modeling Language ◽  
Functional Model ◽  
Design Stage ◽  
Modeling Language ◽  
Embedded Control ◽  
Early Design Stage ◽  
A Performance

To improve the timing related performance of the embedded software of automotive control system, a performance modeling language has been developed based on UML (Unified Modeling Language) using meta-modeling technique. The proposed language consists of three kinds of meta-models used to define the high-level modeling paradigms for software structure, target platform and runtime system respectively. The modeling environment configured by the proposed language and software modules of functional model importation, components allocation, task forming and timing analysis can reuse the existing functional models, add timing requirement as well as resource constraints, and fulfill formal timing analysis at an early design stage. As results, the reliability of the automotive embedded control software can be improved and the development cycle and cost can also be reduced.

Criteria for Best Performance of Pre-Optimized Solid Dampers

2018 ◽  
Vol 141 (4) ◽  
Author(s):  
Chiara Gastaldi ◽  
Muzio M. Gola
Keyword(s):  
High Performance ◽  
Nonlinear Finite Element ◽  
Design Stage ◽  
Experimental Investigations ◽  
Early Design Stage ◽  
Real Contact ◽  
Starting Point ◽  
Definition Of ◽  
Stiffening Effect ◽  
Contact Parameters

This paper furthers recent research by these authors. The starting point is the pre-optimization of solid dampers, which ensures that all dampers bound to “misbehave” are excluded since the early design stage. The authors now enlarge the scope of their investigations to explore those damper configurations selected inside the admissible design area. The purpose of the paper is to present a set of criteria apt to select a damper configuration which not only avoids unwanted situations, but in addition guarantees high performance under different design conditions. The analysis starts with the definition of a set of requirements a high performance damper should meet. In detail, the present investigation seeks to answer the following questions: in the low excitation regime, what is the frequency shift and the stiffening effect each damper can provide? for increasing excitation levels, which damper will start slipping sooner? in the high excitation regime, which damper provides the maximum dissipation? Like pre-optimization, it does not involve nonlinear finite element calculations, and unlike existing optimization procedures, is not linked to a specific set of blades the damper may be coupled to. The numerical prediction of the blade-damper coupled dynamics is here used only for validation purposes. The approach on which this paper rests is fully numerical; however, real contact parameters are taken from extensive experimental investigations made possible by those purposely developed test rigs which are the distinctive mark of the AERMEC Lab of Politecnico di Torino.

Criteria for Best Performance of Pre-Optimized Solid Dampers

2018 ◽  
Author(s):  
Chiara Gastaldi ◽  
Muzio M. Gola
Keyword(s):  
High Performance ◽  
Nonlinear Finite Element ◽  
Design Stage ◽  
Experimental Investigations ◽  
Early Design Stage ◽  
Real Contact ◽  
Starting Point ◽  
Definition Of ◽  
Stiffening Effect ◽  
Contact Parameters

This paper furthers recent research by these authors. The starting point is the pre-optimization of solid dampers, which ensures that all dampers bound to misbehave are excluded since the early design stage. The authors now enlarge the scope of their investigations to explore those damper configurations selected inside the admissible design area. The purpose of the paper is to present a set of criteria apt to select a damper configuration which not only avoids unwanted situations, but in addition guarantees high performance under different design conditions. The analysis starts with the definition of a set of requirements a high performance damper should meet. In detail the present investigation seeks to answer the following questions: – in the low excitation regime, what is the frequency shift and the stiffening effect each damper can provide? – for increasing excitation levels, which damper will start slipping sooner? – in the high excitation regime, which damper provides the maximum dissipation? Like pre-optimization, it does not involve nonlinear Finite Element calculations, and unlike existing optimization procedures, is not linked to a specific set of blades the damper may be coupled to. The numerical prediction of the blade-damper coupled dynamics is here used only for validation purposes. The approach on which this paper rests is fully numerical, however real contact parameters are taken from extensive experimental investigations made possible by those purposely developed test rigs which are the distinctive mark of the AERMEC Lab of Politecnico di Torino.

Approximation of the added resistance of ships with small draft or in ballast condition by empirical formula

2017 ◽  
Vol 233 (1) ◽  
pp. 27-40 ◽  
Author(s):  
Shukui Liu ◽  
Apostolos Papanikolaou
Keyword(s):  
Parametric Study ◽  
Empirical Formula ◽  
Power Estimation ◽  
Design Stage ◽  
Added Resistance ◽  
Regular Waves ◽  
Early Design Stage ◽  
Cruise Ships ◽  
New Formula ◽  
The Impact

An attempt was made to extend and further tune the existing formula for approximating the added resistance in head seas to cover a wider range of speed and to account the impact of loading conditions; a new parameter based on B/ T was introduced after conducting extensive parametric study to capture the influence of draft on the added resistance; the trim effect has also been investigated; Furthermore, the draft effect on the added resistance due to diffraction is further tuned and simplified. The derived formula uses only a few input, including only some ship dimensions to yield an estimation of the added resistance of ships in regular waves. Numerical results show that the added resistance of various ships in head seas at low speeds, as well as the added resistance of tankers in ballast condition and cruise ships, can be properly captured by the new formula. Hence, it meets the demand of fast examination of the minimum power; it can also be used in the early design stage of a ship for power estimation.

Experimental and Numerical Investigation of Seakeeping Performance for Sea-River Ships With Different Hull Fullness

2014 ◽  
Author(s):  
K. V. Kurchukov ◽  
V. G. Platonov ◽  
E. Yu. Katunin ◽  
A. A. Kuznetsov
Keyword(s):  
Coastal Waters ◽  
Experimental Studies ◽  
Critical Issue ◽  
Design Stage ◽  
The Black Sea ◽  
Substantial Part ◽  
Early Design Stage ◽  
Wave Basin ◽  
Seakeeping Performance ◽  
Wave Conditions

Commercial vessels under 5000 dwt, specifically sea-river vessels, constitute a substantial part of the world’s merchant fleet. These vessels are as a rule running between sea, estuary and river ports. Mostly these vessels are restricted in operation by areas, seasons, distance from port of refuge, wind and wave conditions. In this connection the operational safety of such vessels, which are mainly engaged in carriage of oil products, is a critical issue. This paper addresses integrated studies on seakeeping of sea-river vessels starting from the early design stage with preliminary CFD estimates and model experiments in wave basin up to the operational sea trials. The wave conditions for analytical and experimental studies are chosen to be as close as possible to the specific ship profile and expected area of operation. Some conclusions regarding the effect of block coefficient on seakeeping performance of sea-river vessels are made, estimations and experimental data are compared for a ship with extremely large block coefficient and wider operation area (beyond coastal waters), as well as seakeeping performance data recorded at sea during operational voyage of the vessel on the Black sea and Mediterranean sea are given.

scholarly journals Low power and high performance FFT with different radices

2019 ◽  
Vol 8 (2) ◽  
pp. 99
Author(s):  
Md. Zakir Hussain ◽  
Kazi Nikhat Parvin
Keyword(s):  
Low Power ◽  
Communication Systems ◽  
High Performance ◽  
Timing Analysis ◽  
Digital Signal ◽  
Extensive Study ◽  
Low Area ◽  
Booth Multiplier ◽  
Application Systems ◽  
High Performance Application

<p>FFT is one of the most active blocks in digital signal processing and in various field of communication systems. FFT has received significant attention over the past years to increase its capability and versatility. This paper describes an extensive study on trade-off of different radices with different computational elements of butterfly such as adders and multipliers. Finding an efficient radix along with computational elements is the key point to find best suite i.e. high precision, low power and low area applications like radar, filtering, image compression etc. The work also considers the precision and the data format to represent constant value such as Q-point. The proposed FFT architectures not only uphold better solutions for low power and high-performance application systems, but also open up a new research lines. This paper demonstrates that radix-2^3 consumes 43% less LUTs and 17% less power consumption, 40% increase of frequency in radix-2^2 in comparison with radix- 2 algorithm for the combination of CSA with modified booth multiplier and the increment of frequency about 19%, 26% less LUTs consumption and 26% less power in Radix-2^2 when compared to radix-4 with various combination of adder and multiplier. In this work we have used Xilinx 14.7 XST for synthesis and the target device used is Spartan6 XC6SLX100. Simulation is carried out in Xilinx ISIM and also performed timing analysis and generated post-place and route.</p>

Efficient Instruction and Data Caching for High Performance Embedded Processors

1970 ◽  
pp. 9
Author(s):  
A. Ferrerón Labari ◽  
D. Suárez Gracia ◽  
V. Viñals Yúfera
Keyword(s):  
Embedded Systems ◽  
Power Consumption ◽  
Low Power ◽  
Interconnection Networks ◽  
High Performance ◽  
Critical Issue ◽  
Content Management ◽  
Structure Design ◽  
Portable Devices ◽  
On Chip

In the last years, embedded systems have evolved so that they offer capabilities we could only find before in high performance systems. Portable devices already have multiprocessors on-chip (such as PowerPC 476FP or ARM Cortex A9 MP), usually multi-threaded, and a powerful multi-level cache memory hierarchy on-chip. As most of these systems are battery-powered, the power consumption becomes a critical issue. Achieving high performance and low power consumption is a high complexity challenge where some proposals have been already made. Suarez et al. proposed a new cache hierarchy on-chip, the LP-NUCA (Low Power NUCA), which is able to reduce the access latency taking advantage of NUCA (Non-Uniform Cache Architectures) properties. The key points are decoupling the functionality, and utilizing three specialized networks on-chip. This structure has been proved to be efficient for data hierarchies, achieving a good performance and reducing the energy consumption. On the other hand, instruction caches have different requirements and characteristics than data caches, contradicting the low-power embedded systems requirements, especially in SMT (simultaneous multi-threading) environments. We want to study the benefits of utilizing small tiled caches for the instruction hierarchy, so we propose a new design, ID-LP-NUCAs. Thus, we need to re-evaluate completely our previous design in terms of structure design, interconnection networks (including topologies, flow control and routing), content management (with special interest in hardware/software content allocation policies), and structure sharing. In CMP environments (chip multiprocessors) with parallel workloads, coherence plays an important role, and must be taken into consideration.

scholarly journals DSPSR: Digital Signal Processing Software for Pulsar Astronomy

2011 ◽  
Vol 28 (1) ◽  
pp. 1-14 ◽  
Author(s):  
W. van Straten ◽  
M. Bailes
Keyword(s):  
Signal Processing ◽  
Digital Signal Processing ◽  
Graphics Processing Units ◽  
High Performance ◽  
Digital Signal ◽  
General Purpose ◽  
Design Decisions ◽  
Extensive Range ◽  
Processing Software ◽  
Graphics Processing

Abstractdspsr is a high-performance, open-source, object-oriented, digital signal processing software library and application suite for use in radio pulsar astronomy. Written primarily in C++, the library implements an extensive range of modular algorithms that can optionally exploit both multiple-core processors and general-purpose graphics processing units. After over a decade of research and development, dspsr is now stable and in widespread use in the community. This paper presents a detailed description of its functionality, justification of major design decisions, analysis of phase-coherent dispersion removal algorithms, and demonstration of performance on some contemporary microprocessor architectures.

scholarly journals TRACING THE EMERGENCE OF DESIGN PROBLEMS AND THEIR IMPACTS ON THE COMPLEXITY OF ENGINEERING SOLUTIONS

2021 ◽  
Vol 1 ◽  
pp. 3229-3238
Author(s):  
Torben Beernaert ◽  
Pascal Etman ◽  
Maarten De Bock ◽  
Ivo Classen ◽  
Marco De Baar
Keyword(s):  
Large Scale ◽  
Fusion Reactor ◽  
Design Stage ◽  
Engineering Model ◽  
Design Problems ◽  
Nuclear Fusion Reactor ◽  
Early Design Stage ◽  
Iterative Design ◽  
Problems And Solutions ◽  
Emergent Design

AbstractThe design of ITER, a large-scale nuclear fusion reactor, is intertwined with profound research and development efforts. Tough problems call for novel solutions, but the low maturity of those solutions can lead to unexpected problems. If designers keep solving such emergent problems in iterative design cycles, the complexity of the resulting design is bound to increase. Instead, we want to show designers the sources of emergent design problems, so they may be dealt with more effectively. We propose to model the interplay between multiple problems and solutions in a problem network. Each problem and solution is then connected to a dynamically changing engineering model, a graph of physical components. By analysing the problem network and the engineering model, we can (1) derive which problem has emerged from which solution and (2) compute the contribution of each design effort to the complexity of the evolving engineering model. The method is demonstrated for a sequence of problems and solutions that characterized the early design stage of an optical subsystem of ITER.

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