In this paper, a 1T-DRAM based on the junctionless field-effect transistor (JLFET) with a silicon-germanium (SiGe) and silicon (Si) nanotube structure was designed and investigated by using technology computer-aided design (TCAD) simulations. Utilizing bandgap engineering to make a
quantum well in the core–shell structure, the storage pocket is formed by the difference in bandgap energy between SiGe and Si. By applying different voltage conditions at the inner gate and outer gate, excess holes are generated in the storage region by the band-to-band tunneling (BTBT)
mechanism. The BTBT mechanism results in the floating body effect, which is the principle of 1T-DRAM. The varying amount of the accumulated holes in the SiGe region allows differentiating between state “1” and state “0.” Additionally, the outer gate plays a role of
the conventional gate, while the inner gate retains holes in the hold state by applying voltage. Consequently, the optimized SiGe/Si JLFET-based nanotube 1T-DRAM achieved a high sensing margin of 15.4 μA/μm, and a high retention time of 105 ms at a high temperature of 358
K. In addition, it has been verified that a single cycle of 1T-DRAM operations consumes only 33.6 fJ of energy, which is smaller than for previously proposed 1T-DRAMs.
Monolayer and bilayer graphene field effect transistor using Verilog-A