A low dynamic power and low leakage power 90-nm CMOS square-root circuit

With the scaling of technology process, leakage power becomes an increasing portion of total power. Power gating technology is an effective method to suppress the leakage power in VLSI design. When the power gating technique is applied in sequential circuits, such as flip-flops and latches, the data retention is necessary to store the circuit states. A low leakage autonomous data retention flip-flop (ADR-FF) is proposed in this paper. Two high-Vthtransistors are utilized to reduce the leakage power consumption in the sleep mode. The data retention cell is composed of a pair of always powered cross-coupled inverters in the slave latch. No extra control signals and complex operations are needed for controlling the data retention and restoration. The data retention flip-flops are simulated with NCSU 45 nm technology. The postlayout simulation results show that the leakage power of the ADR-FF reduces 51.39% compared with the Mutoh-FF. The active power of the ADR-FF is almost equal to other data retention flip-flops. The average state mode transition time of ADR-FF decreases 55.98%, 51.35%, and 21.07% as compared with Mutoh-FF, Balloon-FF, and Memory-TG-FF, respectively. Furthermore, the area overhead of ADR-FF is smaller than other data retention flip-flops.

Download Full-text

Low leakage power designs of basic standard cells using gate-length biasing

2011 International Conference on Electronics, Communications and Control (ICECC) ◽

10.1109/icecc.2011.6067618 ◽

2011 ◽

Author(s):

Jianping Hu ◽

Jun Wang

Keyword(s):

Leakage Power ◽

Gate Length ◽

Standard Cells ◽

Low Leakage ◽

Basic Standard

Download Full-text

On high noise immunity CMOS design scheme with low leakage power consumption

Proceedings. 7th International Conference on Solid-State and Integrated Circuits Technology, 2004. ◽

10.1109/icsict.2004.1435241 ◽

2005 ◽

Author(s):

M. Abbas ◽

M. Ikeda ◽

K. Asada

Keyword(s):

Power Consumption ◽

Noise Immunity ◽

Leakage Power ◽

High Noise ◽

Design Scheme ◽

Low Leakage ◽

Cmos Design

Download Full-text

Various Logically Optimized D Flip Flop Circuits-A Comparative Study in Submicron Technology

SAMRIDDHI A Journal of Physical Sciences Engineering and Technology ◽

10.18090/samriddhi.v4i2.1503 ◽

2015 ◽

Vol 4 (2) ◽

Author(s):

Abhijit Asthana ◽

Shyam Akashe

Keyword(s):

Comparative Study ◽

Power Dissipation ◽

Leakage Power ◽

Simulation Test ◽

Flip Flop ◽

Chip Area ◽

Low Leakage ◽

Signal Systems ◽

To Come ◽

Power Delay Product

D-Flip Flop (D_FF) is a very important component of various digital, analog and mixed signal systems and designs. It is obvious to come up with optimized D_FF, that cater the needs of low leakage power, less power dissipation, less chip area on the chip and low delays. This paper presents a comparative study of various logically optimized circuits of D_FF using 8T, 11T, 12T and conventional 18T D_FF. The simulation, test circuits, schematics & layouts etc are done on Cadence Virtuoso tool in 180 nm technology. Designs are compared on grounds of power dissipation, leakage power, delays and power delay product.

Download Full-text