Forward discrete probability propagation method for device performance characterization under process variations

Author(s):  
Rasit Onur Topaloglu ◽  
Alex Orailoglu
1999 ◽  
Vol 58 (4) ◽  
pp. 361-373 ◽  
Author(s):  
D.M Oman ◽  
K.M Dugan ◽  
J.L Killian ◽  
V Ceekala ◽  
C.S Ferekides ◽  
...  

Author(s):  
Xing Jin ◽  
Jason V. Clark

In this paper, we present new variation analysis features added to SugarCube. SugarCube is a novice-friendly online CAD tool for exploring the design space of compact MEMS models. Such variation analysis can help to evaluate the bounded effects of unavoidable process variations during the fabrication (such as Young’s modulus, overcut, gap asymmetry, etc.), packaging (such as variations in temperature, expansion coefficients, etc.), and operation (such as variations in voltage sources, etc.). Compared to other software tools for MEMS, the benefits of variation analysis in SugarCube include its comprehensiveness, ease of use, speed, and accessibility. In SugarCube, any geometric, material, or excitation parameter may be easily explored for its effect on device performance. Such analysis is expected to benefit feasibility analyses on process survivability, process yield, and operational robustness. For a couple of test cases, we perform our variation analysis on a micro-scale accelerometer and gyroscope.


2008 ◽  
Author(s):  
Tim Fühner ◽  
Christian Kampen ◽  
Ina Kodrasi ◽  
Alexander Burenkov ◽  
Andreas Erdmann

2015 ◽  
Vol 12 (9-11) ◽  
pp. 1267-1271 ◽  
Author(s):  
Guvenc Ogulgonen ◽  
Talat Ozden ◽  
Ugur Yardim ◽  
Rasit Turan ◽  
Serkan Kincal

Author(s):  
A.C.T. Quah ◽  
C.Q. Chen ◽  
G.B. Ang ◽  
D. Nagalingam ◽  
Y. Li ◽  
...  

Abstract This paper describes 2 case studies where device characterizations using Atomic Force Probe (AFP) nanoprobing, allow for the localization and verification of design weakness and process variations on the Analog-to-Digital (ADC) block that resulted in degraded device performance and severe yield loss. In these cases, the sensitive resistor structures in the ADC block was impacted due to design pattern density interaction with process fabrication steps. In addition, close collaboration with customer was also essential for quick root cause identification, design and process fix.


Author(s):  
Marylyn Bennett-Lilley ◽  
Thomas T.H. Fu ◽  
David D. Yin ◽  
R. Allen Bowling

Chemical Vapor Deposition (CVD) tungsten metallization is used to increase VLSI device performance due to its low resistivity, and improved reliability over other metallization schemes. Because of its conformal nature as a blanket film, CVD-W has been adapted to multiple levels of metal which increases circuit density. It has been used to fabricate 16 MBIT DRAM technology in a manufacturing environment, and is the metallization for 64 MBIT DRAM technology currently under development. In this work, we investigate some sources of contamination. One possible source of contamination is impurities in the feed tungsten hexafluoride (WF6) gas. Another is particle generation from the various reactor components. Another generation source is homogeneous particle generation of particles from the WF6 gas itself. The purpose of this work is to investigate and analyze CVD-W process-generated particles, and establish a particle characterization methodology.


Author(s):  
F. M. Ross ◽  
R. Hull ◽  
D. Bahnck ◽  
J. C. Bean ◽  
L. J. Peticolas ◽  
...  

We describe an investigation of the electrical properties of interfacial dislocations in strained layer heterostructures. We have been measuring both the structural and electrical characteristics of strained layer p-n junction diodes simultaneously in a transmission electron microscope, enabling us to correlate changes in the electrical characteristics of a device with the formation of dislocations.The presence of dislocations within an electronic device is known to degrade the device performance. This degradation is of increasing significance in the design and processing of novel strained layer devices which may require layer thicknesses above the critical thickness (hc), where it is energetically favourable for the layers to relax by the formation of misfit dislocations at the strained interfaces. In order to quantify how device performance is affected when relaxation occurs we have therefore been investigating the electrical properties of dislocations at the p-n junction in Si/GeSi diodes.


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