A Delay-Adjustable, Self-Testable Flip-Flop for Soft-Error Tolerability and Delay-Fault Testability

2021 ◽  
Vol 26 (6) ◽  
pp. 1-12
Author(s):  
Dave Y.-W. Lin ◽  
Charles H.-P. Wen
Keyword(s):  
Energy Levels ◽  
Soft Error ◽  
Test Method ◽  
Experimental Result ◽  
Flip Flop ◽  
Area Overhead ◽  
Design Reliability ◽  
Radiation Hardened ◽  
Self Test ◽  
Built In Self Test

As the demand of safety-critical applications (e.g., automobile electronics) increases, various radiation-hardened flip-flops are proposed for enhancing design reliability. Among all flip-flops, Delay-Adjustable D-Flip-Flop (DAD-FF) is specialized in arbitrarily adjusting delay in the design to tolerate soft errors induced by different energy levels. However, due to a lack of testability on DAD-FF, its soft-error tolerability is not yet verified, leading to uncertain design reliability. Therefore, this work proposes Delay-Adjustable, Self-Testable Flip-Flop (DAST-FF), built on top of DAD-FF with two extra MUXs (one for scan test and the other for latching-delay verification) to achieve both soft-error tolerability and testability. Meanwhile, a built-in self-test method is also developed on DAST-FFs to verify the cumulative latching delay before operation. The experimental result shows that for a design with 8,802 DAST-FFs, the built-in self-test method only takes 946 ns to ensure the soft-error tolerability. As to the testability, the enhanced scan capability can be enabled by inserting one extra transmission gate into DAST-FF with only 4.5 area overhead.

scholarly journals Categorization and SEU Fault Simulations of Radiation-Hardened-by-Design Flip-Flops

Electronics ◽  
2021 ◽  
Vol 10 (13) ◽  
pp. 1572
Author(s):  
Ehab A. Hamed ◽  
Inhee Lee
Keyword(s):  
Soft Error ◽  
Error Tolerance ◽  
Cmos Process ◽  
Flip Flop ◽  
Single Event Upsets ◽  
Area Overhead ◽  
Fair Comparison ◽  
Reference Design ◽  
Radiation Hardened ◽  
Radiation Hardened By Design

In the previous three decades, many Radiation-Hardened-by-Design (RHBD) Flip-Flops (FFs) have been designed and improved to be immune to Single Event Upsets (SEUs). Their specifications are enhanced regarding soft error tolerance, area overhead, power consumption, and delay. In this review, previously presented RHBD FFs are classified into three categories with an overview of each category. Six well-known RHBD FFs architectures are simulated using a 180 nm CMOS process to show a fair comparison between them while the conventional Transmission Gate Flip-Flop (TGFF) is used as a reference design for this comparison. The results of the comparison are analyzed to give some important highlights about each design.

A low-cost built-in self-test method for thermally actuated resistive MEMS sensors

2013 ◽  
Vol 194 ◽  
pp. 8-15 ◽  
Author(s):  
O. Legendre ◽  
H. Bertin ◽  
H. Mathias ◽  
S. Megherbi ◽  
J. Juillard ◽  
...  
Keyword(s):  
Low Cost ◽  
Test Method ◽  
Mems Sensors ◽  
Self Test ◽  
Built In Self Test ◽  
Thermally Actuated

scholarly journals BIST-based Testing and Diagnosis of LUTs in SRAM-based FPGAs

2018 ◽  
Vol 1 (4) ◽  
Author(s):  
Hadi Jahanirad ◽  
Hanieh Karam
Keyword(s):  
Cmos Technology ◽  
Test Methods ◽  
Leakage Power ◽  
Digital Systems ◽  
Area Overhead ◽  
Logic Block ◽  
Fpga Chip ◽  
Simulation Results ◽  
Self Test ◽  
Built In Self Test

FPGA chips have wide applications in nowadays digital systems. Because of fault prone nature of FPGA chips, testing of them is one of the major challenges for designers. Among various test methods, the Built-in Self-Test (BIST) based ones have shown good performance. In this paper, we presented a BIST-based approach to test LUTs as most vulnerable part of FPGA chip. The BIST-based approach is off-line and has been accomplished within two FPGA configurations. Each configurable logic block (CLB) can be tested independently and there is no handshaking among various CLBs' BIST cores. The proposed BIST architecture has been simulated in HSPICE based on 45-nm CMOS technology. Simulation results shown 100% coverage for single stuck at faults along with 19% area overhead due to additional BIST hardware and 25% increase in leakage power.

scholarly journals A BIST Methodology to test CLB Resources on an SRAM-Based FPGA using Complementary Gates Configuration

2020 ◽  
Vol 9 (12) ◽  
pp. 217-220
Keyword(s):  
Field Programmable Gate Array ◽  
Test Pattern ◽  
Fault Coverage ◽  
Area Overhead ◽  
Field Programmable ◽  
Self Test ◽  
Gate Array ◽  
Built In Self Test ◽  
Pattern Generators ◽  
Logic Blocks

This paper primarily focuses on designing a new Built in self test (BIST) methodology to test the configurable logic blocks (CLBs) which is the heart of field programmable gate array (FPGA). The proposed methodology targets stuck-at-0/1 faults on a RAM cell in an LUT which constitutes about 90% of the total faults in the CLBs. No extra area overhead is needed to accommodate the test pattern generators (TPGs) and output responses analyzers (ORAs) as they are realized by the already existing configurable resources on the FPGA.A group of CLBs chosen as block under test (BUT) are configured as complementary gates (AND/NAND, OR/NOR, XOR/XNOR) to successfully test the aforementioned faults. The proposed BIST structure when implemented on Xilinx Virtex-4 FPGA proved 100% fault coverage and minimized test configurations.

Built-in Self-Test Design for Fault Detection of MUXFXs in SRAM-Based FPGAs

2010 ◽  
Vol 39 ◽  
pp. 220-225
Author(s):  
Sheng Hong ◽  
Wen Hui Tao ◽  
Yun Ping Qi ◽  
Cheng Gao ◽  
Xiao Zhang Liu ◽  
...  
Keyword(s):  
Fault Detection ◽  
Test Pattern ◽  
Pattern Generator ◽  
Test Design ◽  
Output Response ◽  
Area Overhead ◽  
Self Test ◽  
Built In Self Test ◽  
Logic Blocks

This paper proposes a built-in self-test (BIST) design for MUXFXs in SRAM-based FPGAs. This approach can test both the interconnect resources and MUXFXs in the configurable logic blocks (CLBs). Because the test pattern generator (TPG) and output response analyzer (ORA)are configured by existing CLBs in FPGAs, no extra area overhead is needed for the proposed BIST structure. Open/short , stuck on/off faults in PSs, and stuck-at-0/1 faults in MUXFXs will be detected through the target fault detection/diagnosis of the proposed BIST structure.

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