Electrical Characterization of Silicon-on-Insulator Wafers Using Photo-Conductance Decay (PCD) Method

Abstract Scanning capacitance microscopy (SCM) has been used in electrical failure analysis (EFA) to isolate failing silicon transistors on silicon-on-insulator (SOI) substrates. With the shrinking device geometry and increasing layout complexity, the defects in transistors are often non-visual and require detailed electrical analysis to pinpoint the defect signature. This paper demonstrates the use of SCM technique for EFA on SOI device substrates, as well as using this technique to isolate defective contacts in a relatively large-area scan of 25µm x 25µm. We also performed dC/dV electrical characterization of defective transistors, and correlated the data from SCM technique and electrical data from nano-probing to locate failing transistors.

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Ultrathin Low Energy Simox for Low Cost, High Density Applications

MRS Proceedings ◽

10.1557/proc-316-1053 ◽

1993 ◽

Vol 316 ◽

Cited By ~ 1

Author(s):

Fereydoon Namavar ◽

N.M. Kalkhoran ◽

A. Cremins

Keyword(s):

Low Cost ◽

Electrical Characterization ◽

Low Energy ◽

Silicon On Insulator ◽

Great Promise ◽

Fully Depleted ◽

Device Structures ◽

Radiation Hard ◽

Standard Energy

ABSTRACTSilicon-on-insulator (SOI) materials made by standard energy (150 to 200 keV) separation by implantation of oxygen (SIMOX) processes have shown great promise for meeting the needs of radiation-hard microelectronics. Since much smaller doses are required, low energy SIMOX (LES) reduces cost, improves radiation hardness, and increases the throughput of any ion implanter. The process can also produce high quality thin SIMOX structures that are of particular interest for fully depleted and submicron device structures. In this paper, we address the formation as well as the material and electrical characterization of LES wafers and compare them with standard SIMOX wafers.

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Electrical characterization of air-bridge-structured silicon wires fabricated by micromachining of silicon-on-insulator substrate

Digest of Papers. Microprocesses and Nanotechnology '99. 1999 International Microprocesses and Nanotechnology Conference ◽

10.1109/imnc.1999.797515 ◽

2003 ◽

Author(s):

H. Fujii ◽

S. Kanemaru ◽

T. Matsukawa ◽

J. Itoh

Keyword(s):

Electrical Characterization ◽

Silicon On Insulator ◽

Insulator Substrate

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Etching properties and electrical characterization of surfaces of silicon-on-insulator substrates in presence of halogens

Journal of Applied Physics ◽

10.1063/1.3695455 ◽

2012 ◽

Vol 111 (6) ◽

pp. 064912 ◽

Cited By ~ 1

Author(s):

A. Abbadie ◽

G. Hamaide ◽

D. Mariolle ◽

M. Chaupin ◽

F. Brunier ◽

...

Keyword(s):

Electrical Characterization ◽

Silicon On Insulator

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Electrical Characterization of Laser/Energy-Beam Recrystallized Thin Film Silicon-On-Insulator (SOI)

MRS Proceedings ◽

10.1557/proc-33-139 ◽

1984 ◽

Vol 33 ◽

Author(s):

El-Hang Lee ◽

D. J. Ruprecht

Keyword(s):

Thin Film ◽

Epitaxial Growth ◽

Electrical Transport ◽

Structural Variation ◽

Laser Energy ◽

Electrical Characterization ◽

Silicon On Insulator ◽

Electrical Transport Properties ◽

Energy Beam

ABSTRACTSpreading resistance has been measured for various types of grain boundaries formed on graphite heater recrystallized SOI samples (G-SOI) or laser strip beam-recrystallized SOI samples (L-SOI) in order to identify the characteristic relation between the morphological/structural variation of the boundary defects and their electrical transport properties. In general, the resistance values across L-SOI sub-boundaries are higher than those across G-SOI sub-boundaries. TEM analyses reveal evidences of higher degree of crystallographic mismatch (up to 10°) in L-SOI sub-boundaries than that (1 – 2°) in G-SOI sub-boundaries. The measurement also revealed the evidences of counter-doping near the seed areas where the epitaxial growth initiated.

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