scholarly journals Radix-2α/4β Building Blocks for Efficient VLSI’s Higher Radices Butterflies Implementation

VLSI Design ◽  
2014 ◽  
Vol 2014 ◽  
pp. 1-13 ◽  
Author(s):  
Marwan A. Jaber ◽  
Daniel Massicotte
Keyword(s):  
Fourier Transform ◽  
Parallel Processing ◽  
Fast Fourier Transform ◽  
Critical Path ◽  
Building Blocks ◽  
Circuit Diagram ◽  
Fft Processor ◽  
Building Process ◽  
Complex Multiplier

This paper describes an embedded FFT processor where the higher radices butterflies maintain one complex multiplier in its critical path. Based on the concept of a radix-r fast Fourier factorization and based on the FFT parallel processing, we introduce a new concept of a radix-r Fast Fourier Transform in which the concept of the radix-r butterfly computation has been formulated as the combination of radix-2α/4β butterflies implemented in parallel. By doing so, the VLSI butterfly implementation for higher radices would be feasible since it maintains approximately the same complexity of the radix-2/4 butterfly which is obtained by block building of the radix-2/4 modules. The block building process is achieved by duplicating the block circuit diagram of the radix-2/4 module that is materialized by means of a feed-back network which will reuse the block circuit diagram of the radix-2/4 module.

scholarly journals An Ultra-Area-Efficient 1024-Point In-Memory FFT Processor

Micromachines ◽  
2019 ◽  
Vol 10 (8) ◽  
pp. 509 ◽  
Author(s):  
Hasan Erdem Yantır ◽  
Wenzhe Guo ◽  
Ahmed M. Eltawil ◽  
Fadi J. Kurdahi ◽  
Khaled Nabil Salama
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Current Literature ◽  
Power Efficiency ◽  
Design Principles ◽  
The Other ◽  
Area Efficiency ◽  
Processor Architectures ◽  
Fft Processor ◽  
Area Efficient

Current computation architectures rely on more processor-centric design principles. On the other hand, the inevitable increase in the amount of data that applications need forces researchers to design novel processor architectures that are more data-centric. By following this principle, this study proposes an area-efficient Fast Fourier Transform (FFT) processor through in-memory computing. The proposed architecture occupies the smallest footprint of around 0.1 mm 2 inside its class together with acceptable power efficiency. According to the results, the processor exhibits the highest area efficiency ( FFT / s / area ) among the existing FFT processors in the current literature.

scholarly journals Double Precision Floating Point Fft Processor using Vedic Mathematics

2019 ◽  
Vol 8 (4) ◽  
pp. 8533-8538
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Floating Point ◽  
Double Precision ◽  
Power Efficient ◽  
Vedic Mathematics ◽  
Communication Signal ◽  
Fft Processor ◽  
Complex Multiplications ◽  
Point Fast Fourier Transform

There should be rapid, efficient and simple process for every scenario now a day. To compute the N point DFT, Fast Fourier Transform (FFT) is a productive algorithm. It has great applications in communication, signal and image processing and instrumentation. In the implementation of FFT one of the challenges is the complex multiplications, so to make this process rapid and simple it’s necessary for a multiplier to be fast and power efficient. To tackle this problem Karatsuba sutra and Nikhilam sutra are an efficient method of multiplication in Vedic Mathematics. This paper will present a design methodology of Double Precision Floating Point Fast Fourier Transform (FFT) Processor.The execution time and complexity can be reduced by the algorithm which is there in Vedic.The main aim is to make FFT Processor process rapid and simple by designing a multiplier which is fast and power efficient by using double precision floating point and Vedic Mathematics concepts.

scholarly journals A Novel Address Scheme for Continuous-Flow Parallel Memory-Based Real-Valued FFT Processor

Electronics ◽  
2019 ◽  
Vol 8 (9) ◽  
pp. 1042 ◽  
Author(s):  
Min Yuan ◽  
Zhenguo Ma ◽  
Feng Yu ◽  
Qianjian Xing
Keyword(s):  
Fourier Transform ◽  
Parallel Processing ◽  
Continuous Flow ◽  
State Of The Art ◽  
Signal Flow Graph ◽  
Normal Order ◽  
Variable Size ◽  
Flow Graph ◽  
Parallel Memory ◽  
Fft Processor

In this article, we present a modified constant-geometry based signal flow graph for memory-based real-valued fast Fourier transform architecture. Without an extra permutation, the corresponding address scheme solves the memory conflict and achieves continuous-flow operation with the minimal memory and computation cycles requirement when compared to the state-of-the-art designs. Besides, the address scheme meets the constraint of in-place operation, concurrent I/O, normal-order I/O, variable size, and parallel processing. The experimental results demonstrate the resource and frequency efficiency of the proposed address scheme.

Pipelined Fast Fourier Transform (FFT) Processor Power Optimization

2019 ◽  
Author(s):  
Siti Lailatul Mohd Hassan ◽  
Nasri Sulaiman ◽  
Ili Shairah Abdul Halim ◽  
A'zraa Ahfzan Ab Rahim ◽  
Noor Ezan Abdullah
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Power Optimization ◽  
Fft Processor
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