scholarly journals Static quantised radix-2 fast Fourier transform (FFT)/inverse FFT processor for constraints analysis

2013 ◽  
Vol 101 (2) ◽  
pp. 231-240 ◽  
Author(s):  
Rozita Teymourzadeh ◽  
Memtode Jim Abigo ◽  
Mok Vee Hoong
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Fft Processor

scholarly journals An Ultra-Area-Efficient 1024-Point In-Memory FFT Processor

Micromachines ◽  
2019 ◽  
Vol 10 (8) ◽  
pp. 509 ◽  
Author(s):  
Hasan Erdem Yantır ◽  
Wenzhe Guo ◽  
Ahmed M. Eltawil ◽  
Fadi J. Kurdahi ◽  
Khaled Nabil Salama
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Current Literature ◽  
Power Efficiency ◽  
Design Principles ◽  
The Other ◽  
Area Efficiency ◽  
Processor Architectures ◽  
Fft Processor ◽  
Area Efficient

Current computation architectures rely on more processor-centric design principles. On the other hand, the inevitable increase in the amount of data that applications need forces researchers to design novel processor architectures that are more data-centric. By following this principle, this study proposes an area-efficient Fast Fourier Transform (FFT) processor through in-memory computing. The proposed architecture occupies the smallest footprint of around 0.1 mm 2 inside its class together with acceptable power efficiency. According to the results, the processor exhibits the highest area efficiency ( FFT / s / area ) among the existing FFT processors in the current literature.

scholarly journals Radix-2α/4β Building Blocks for Efficient VLSI’s Higher Radices Butterflies Implementation

VLSI Design ◽  
2014 ◽  
Vol 2014 ◽  
pp. 1-13 ◽  
Author(s):  
Marwan A. Jaber ◽  
Daniel Massicotte
Keyword(s):  
Fourier Transform ◽  
Parallel Processing ◽  
Fast Fourier Transform ◽  
Critical Path ◽  
Building Blocks ◽  
Circuit Diagram ◽  
Fft Processor ◽  
Building Process ◽  
Complex Multiplier

This paper describes an embedded FFT processor where the higher radices butterflies maintain one complex multiplier in its critical path. Based on the concept of a radix-r fast Fourier factorization and based on the FFT parallel processing, we introduce a new concept of a radix-r Fast Fourier Transform in which the concept of the radix-r butterfly computation has been formulated as the combination of radix-2α/4β butterflies implemented in parallel. By doing so, the VLSI butterfly implementation for higher radices would be feasible since it maintains approximately the same complexity of the radix-2/4 butterfly which is obtained by block building of the radix-2/4 modules. The block building process is achieved by duplicating the block circuit diagram of the radix-2/4 module that is materialized by means of a feed-back network which will reuse the block circuit diagram of the radix-2/4 module.

scholarly journals Double Precision Floating Point Fft Processor using Vedic Mathematics

2019 ◽  
Vol 8 (4) ◽  
pp. 8533-8538
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Floating Point ◽  
Double Precision ◽  
Power Efficient ◽  
Vedic Mathematics ◽  
Communication Signal ◽  
Fft Processor ◽  
Complex Multiplications ◽  
Point Fast Fourier Transform

There should be rapid, efficient and simple process for every scenario now a day. To compute the N point DFT, Fast Fourier Transform (FFT) is a productive algorithm. It has great applications in communication, signal and image processing and instrumentation. In the implementation of FFT one of the challenges is the complex multiplications, so to make this process rapid and simple it’s necessary for a multiplier to be fast and power efficient. To tackle this problem Karatsuba sutra and Nikhilam sutra are an efficient method of multiplication in Vedic Mathematics. This paper will present a design methodology of Double Precision Floating Point Fast Fourier Transform (FFT) Processor.The execution time and complexity can be reduced by the algorithm which is there in Vedic.The main aim is to make FFT Processor process rapid and simple by designing a multiplier which is fast and power efficient by using double precision floating point and Vedic Mathematics concepts.

Pipelined Fast Fourier Transform (FFT) Processor Power Optimization

2019 ◽  
Author(s):  
Siti Lailatul Mohd Hassan ◽  
Nasri Sulaiman ◽  
Ili Shairah Abdul Halim ◽  
A'zraa Ahfzan Ab Rahim ◽  
Noor Ezan Abdullah
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Power Optimization ◽  
Fft Processor

Design and Implementation of Fast Fourier Transform (FFT) using VHDL Code

2018 ◽  
Vol 6 (8) ◽  
pp. 268
Author(s):  
Akarshika Singhal ◽  
Anjana Goen ◽  
Tanu Trushna Mohapatrara
Keyword(s):  
Image Processing ◽  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Discrete Fourier Transform ◽  
Digital Signal ◽  
Frequency Division ◽  
Signal And Image Processing ◽  
Design And Implementation ◽  
Fft Processor ◽  
Vhdl Code

The Discrete Fourier Transform (DFT) can be implemented very fast using Fast Fourier Transform (FFT). It is one of the finest operation in the area of digital signal and image processing. FFT is a luxurious operation in terms of MAC. To achieve FFT calculation with a many points and with maximum number of samples the MACs requirement could not be matched by efficient hardware’s like DSP. A parallel and pipelined Fast Fourier Transform (FFT) processor for use in the Orthogonal Frequency division Multiplexer (OFDM) and WLAN, unlike being stored in the traditional ROM. The twiddle factors in our pipelined FFT processor can be accessed directly. In this paper, we present the implementation of fast algorithms for the DFT for evaluating their performance. The performance of this algorithm by implementing them on the Xillinx 9.2i Spartan 3E FPGAs  by developing our own FFT processor architecture.

ROM REDUCTION FOR OFDM SYSTEM USING TIME-STEALING STRATEGY

2006 ◽  
Vol 15 (06) ◽  
pp. 907-921
Author(s):  
CHUN-CHING WANG ◽  
YIH-CHUAN LIN ◽  
CHI-YIN LIN
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Communication Systems ◽  
High Performance ◽  
Digital Audio ◽  
Fft Processor ◽  
Robust Transmission ◽  
Video Broadcast ◽  
Audio Video ◽  
Combinational Logic Circuit

Modern communication systems frequently exploit the OFDM (Orthogonal Frequency Division Multiplex) technique to obtain a highly robust transmission of multimedia information, such as digital audio/video broadcast. OFDM and most of the other multimedia compression techniques usually require expensive computations, e.g., FFT (Fast Fourier Transform) and IMDCT (Inverse Modified Discrete Cosine Transform) processing. Traditionally, designing FFT and IMDCT separately involves a significant amount of redundancy in hardware. To reduce the required hardware, this investigation proposes a new ROM-sharing design for storing both FFT twiddle factors and IMDCT coefficients in a DAB (Digital Audio Broadcasting) receiver. We first analyze the correlation between FFT operations and IMDCT operations, and then the combinational logic circuit in the FFT processor is modified such that both IMDCT coefficients and FFT twiddle factors can be obtained simultaneously from a shared ROM. This design can also be applied for computing IFFT (Inverse Fast Fourier Transform) and MDCT for DAB transmitter. Compared with the traditional design using separate module scheme, our design does not need extra ROM for IMDCT/MDCT modules. Therefore, the new scheme offers superior solution for combining high-performance FFT (IFFT) operation and IMDCT (MDCT) operation.

scholarly journals Signal-to-noise Ratio Study on Pipelined Fast Fourier Transform Processor

2018 ◽  
Vol 7 (2) ◽  
pp. 230-235
Author(s):  
S. L. M. Hassan ◽  
N. Sulaiman ◽  
S. S. Shariffudin ◽  
T. N. T. Yaakub
Keyword(s):  
Fourier Transform ◽  
Fast Fourier Transform ◽  
Signal To Noise Ratio ◽  
Data Communication ◽  
Digital Signal ◽  
Signal To Noise ◽  
Digital Video Broadcasting ◽  
Video Broadcasting ◽  
Fft Processor ◽  
Noise Ratio

Fast Fourier transform (FFT) processor is a prevailing tool in converting signal in time domain to frequency domain. This paper provides signal-to-noise ratio (SNR) study on 16-point pipelined FFT processor implemented on field-programable gate array (FPGA). This processor can be used in vast digital signal applications such as wireless sensor network, digital video broadcasting and many more. These applications require accuracy in their data communication part, that is why SNR is an important analysis. SNR is a measure of signal strength relative to noise. The measurement is usually in decibles (dB). Previously, SNR studies have been carried out in software simulation, for example in Matlab. However, in this paper, pipelined FFT and SNR modules are developed in hardware form. SNR module is designed in Modelsim using Verilog code before implemented on FPGA board. The SNR module is connected directly to the output of the pipelined FFT module. Three different pipelined FFT with different architectures were studied. The result shows that SNR for radix-8 and R4SDC FFT architecture design are above 40dB, which represent a very excellent signal. SNR module on the FPGA and the SNR results of different pipelined FFT architecture can be consider as the novelty of this paper.

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