scholarly journals Crypto-Stego-Real-Time (CSRT) System for Secure Reversible Data Hiding

VLSI Design ◽  
2018 ◽  
Vol 2018 ◽  
pp. 1-8 ◽  
Author(s):  
Latika Desai ◽  
Suresh Mali
Keyword(s):  
Real Time ◽  
Communication Networks ◽  
Data Hiding ◽  
Information Transfer ◽  
Signal To Noise Ratio ◽  
Wireless Communication Network ◽  
Hardware Implementations ◽  
Dct Domain ◽  
Field Programmable ◽  
Application Data

Due to demand of information transfer through higher speed wireless communication network, it is time to think about security of important information to be transferred. Further, as these communication networks are part of open channel, to preserve the security of any Critical Information (CI) is really a challenging task in any real-time application. Data hiding techniques give more security and robustness of important CI against encryption or cryptographic software solutions. However, hardwired approach exhibits better solution not only in terms of reduction of complexity but also in terms of adaptive real-time output. This paper demonstrates frequency, Discrete Cosine Transform (DCT) domain Steganographic data hiding hardware solution for secret communication called Crypto-Stego-Real-Time (CSRT) System. The challenge is to design a secure algorithm keeping reliability of minimum distortion of original cover signal while embedding considerable amount of CI. Field Programmable Gate Array (FPGA) implementation shown in this paper is more secure, robust, and fast. Pipelining process while embedding enhances the speed of embedding, optimizes the memory utilization, and gives better Peak Signal to Noise Ratio (PSNR) and high robustness. Practically implemented hardware Steganographic solutions shown in this paper also give better performance than that of the current state-of-the-art hardware implementations.

scholarly journals Development of an FPGA-based realtime DAQ system for axion haloscope experiments

2021 ◽  
Vol 16 (11) ◽  
pp. T11008
Author(s):  
M.J. Lee ◽  
B.R. Ko ◽  
S. Ahn
Keyword(s):  
Real Time ◽  
Data Transfer ◽  
Signal To Noise Ratio ◽  
Frequency Resolution ◽  
Fast Fourier Transformation ◽  
Time Data ◽  
Real Time Data ◽  
Field Programmable ◽  
Analysis Window ◽  
Pseudo Data

Abstract A real-time Data Acquisition (DAQ) system for the CULTASK axion haloscope experiment was constructed and tested. The CULTASK is an experiment to search for cosmic axions using resonant cavities, to detect photons from axion conversion through the inverse Primakoff effect in a few GHz frequency range in a very high magnetic field and at an ultra low temperature. The constructed DAQ system utilizes a Field Programmable Gate Array (FPGA) for data processing and Fast Fourier Transformation. This design along with a custom Ethernet packet designed for real-time data transfer enables 100% DAQ efficiency, which is the key feature compared with a commercial spectrum analyzer. This DAQ system is optimally designed for RF signal detection in the axion experiment, with 100 Hz frequency resolution and 500 kHz analysis window. The noise level of the DAQ system averaged over 100,000 measurements is around -111.7 dBm. From a pseudo-data analysis, an improvement of the signal-to-noise ratio due to repeating and averaging the measurements using this real-time DAQ system was confirmed.

Real-Time Implementation of MAD-Based RFI Excision on FPGA

2019 ◽  
Vol 08 (01) ◽  
pp. 1940006 ◽  
Author(s):  
Kaushal D. Buch ◽  
Kishor Naik ◽  
Swapnil Nalawade ◽  
Shruti Bhatporia ◽  
Yashwant Gupta ◽  
...  
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
Signal To Noise Ratio ◽  
Radio Frequency Interference ◽  
Challenging Problem ◽  
Signal To Noise ◽  
Absolute Deviation ◽  
Field Programmable ◽  
Wideband Radio ◽  
Robust Variant

Radio Frequency Interference (RFI) excision in wideband radio telescope receivers is gaining significance due to increasing levels of manmade RFI and operation outside the protected radio astronomy bands. The effect of RFI on astronomical data can be significantly reduced through real-time excision. In this paper, Median Absolute Deviation (MAD) is used for excising signals corrupted by strong impulsive interference. MAD estimation requires recursive median calculation which is a computationally challenging problem for real-time excision. This challenge is addressed by implementation of a histogram-based technique for MAD computation. The architecture is developed and optimized for Field Programmable Gate Array (FPGA) implementation. The design of a more robust variant of MAD called Median-of-MAD (MoM) is described. The architecture of MAD and MoM techniques and subsequent optimization allows for four RFI excision blocks on a single Xilinx Virtex-5 FPGA. These techniques have been tested on the GMRT wideband backend (GWB) processing a maximum of 400[Formula: see text]MHz bandwidth and the results show significant improvement in the signal-to-noise ratio (SNR).

scholarly journals An intelligent transportation system for forecasting wireless communication network issues with cyber attacks

2021 ◽  
Author(s):  
M. Khaleel Ullah Khan ◽  
Keyword(s):  
Wireless Communication ◽  
Real Time ◽  
Communication Networks ◽  
Intelligent Transportation System ◽  
Intelligent Transportation ◽  
Transportation System ◽  
Cyber Attacks ◽  
Wireless Communication Networks ◽  
Cyber Attack ◽  
Wireless Communication Network

This paper propose a method to design an “Intelligent Transportation System” for forecasting wireless communication network issues with cyber attacks. Wireless communication networks(WCN) is a broadly classified and critical gateway for any communication devices because the wireless communication networks is operated at various frequency ranges in different locations. In order to maintain its performance and also to prevent any attacks due to its high data handling, we need an Intelligent transportation system (ITS) to analyse and detect the cyber-attacks before going to implement it in real time transportation. In general wireless communication networks is an IEEE 802.11 standard which can be operated at physical Transfer control protocol/Internet protocol(TCP/IP) layer as well OSI model. In this paper a novel approach to design, analyse and detect cyber-attacks is proposed for wireless communication networks transport system, called Intelligent transportation system (ITS) based cyber-attack detection. Stacked firewall system is used for reducing fake attacks and detecting real time attacks in transportation system. Hence any fake attacks or real time attacks captured by the ITS will be informed to the system controller to make decision to whether it is a false-positive or real attack. ITS is the main process of the stacked firewall system which in turn take responsible to control, maintain, and prevent any cyber-attack.

Determination of the Best Emulsion for the Microscopy of Crystals

1981 ◽  
Vol 39 ◽  
pp. 32-33
Author(s):  
David A. Grano ◽  
Kenneth H. Downing
Keyword(s):  
Spatial Frequency ◽  
Information Transfer ◽  
Signal To Noise Ratio ◽  
Experimental Situation ◽  
Photographic Emulsion ◽  
Modulation Transfer ◽  
Signal To Noise ◽  
Frequency Space ◽  
Noise Ratio

The retrieval of high-resolution information from images of biological crystals depends, in part, on the use of the correct photographic emulsion. We have been investigating the information transfer properties of twelve emulsions with a view toward 1) characterizing the emulsions by a few, measurable quantities, and 2) identifying the “best” emulsion of those we have studied for use in any given experimental situation. Because our interests lie in the examination of crystalline specimens, we've chosen to evaluate an emulsion's signal-to-noise ratio (SNR) as a function of spatial frequency and use this as our critereon for determining the best emulsion.The signal-to-noise ratio in frequency space depends on several factors. First, the signal depends on the speed of the emulsion and its modulation transfer function (MTF). By procedures outlined in, MTF's have been found for all the emulsions tested and can be fit by an analytic expression 1/(1+(S/S0)2). Figure 1 shows the experimental data and fitted curve for an emulsion with a better than average MTF. A single parameter, the spatial frequency at which the transfer falls to 50% (S0), characterizes this curve.

Real-time signal processing in field programmable gate array based digital gamma-ray spectrometer

2020 ◽  
Vol 91 (10) ◽  
pp. 104707
Author(s):  
Yinyu Liu ◽  
Hao Xiong ◽  
Chunhui Dong ◽  
Chaoyang Zhao ◽  
Quanfeng Zhou ◽  
...  
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
Field Programmable Gate Array ◽  
Gamma Ray ◽  
Time Signal ◽  
Gamma Ray Spectrometer ◽  
Field Programmable ◽  
Gate Array ◽  
Real Time Signal Processing

Accelerating laser processes with a smart two-dimensional polygon mirror scanner for ultra-fast beam deflection

2021 ◽  
Vol 0 (0) ◽  
Author(s):  
Florian Roessler ◽  
André Streek
Keyword(s):  
Energy Distribution ◽  
Real Time ◽  
Laser Processing ◽  
High Speed ◽  
Beam Deflection ◽  
Two Dimensional ◽  
Heat Accumulation ◽  
Field Programmable ◽  
Drill Holes ◽  
Average Laser

Abstract In laser processing, the possible throughput is directly scaling with the available average laser power. To avoid unwanted thermal damage due to high pulse energy or heat accumulation during MHz-repetition rates, energy distribution over the workpiece is required. Polygon mirror scanners enable high deflection speeds and thus, a proper energy distribution within a short processing time. The requirements of laser micro processing with up to 10 kW average laser powers and high scan speeds up to 1000 m/s result in a 30 mm aperture two-dimensional polygon mirror scanner with a patented low-distortion mirror configuration. In combination with a field programmable gate array-based real-time logic, position-true high-accuracy laser switching is enabled for 2D, 2.5D, or 3D laser processing capable to drill holes in multi-pass ablation or engraving. A special developed real-time shifter module within the high-speed logic allows, in combination with external axis, the material processing on the fly and hence, processing of workpieces much larger than the scan field.

scholarly journals The Design of a 2D Graphics Accelerator for Embedded Systems

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 469
Author(s):  
Hyun Woo Oh ◽  
Ji Kwang Kim ◽  
Gwan Beom Hwang ◽  
Seung Eun Lee
Keyword(s):  
Embedded Systems ◽  
Embedded System ◽  
Real Time ◽  
Line Drawing ◽  
Cmos Process ◽  
Embedded Processor ◽  
Processor Core ◽  
Field Programmable ◽  
The Embedded System ◽  
Graphics Processing

Recently, advances in technology have enabled embedded systems to be adopted for a variety of applications. Some of these applications require real-time 2D graphics processing running on limited design specifications such as low power consumption and a small area. In order to satisfy such conditions, including a specific 2D graphics accelerator in the embedded system is an effective method. This method reduces the workload of the processor in the embedded system by exploiting the accelerator. The accelerator assists the system to perform 2D graphics processing in real-time. Therefore, a variety of applications that require 2D graphics processing can be implemented with an embedded processor. In this paper, we present a 2D graphics accelerator for tiny embedded systems. The accelerator includes an optimized line-drawing operation based on Bresenham’s algorithm. The optimized operation enables the accelerator to deal with various kinds of 2D graphics processing and to perform the line-drawing instead of the system processor. Moreover, the accelerator also distributes the workload of the processor core by removing the need for the core to access the frame buffer memory. We measure the performance of the accelerator by implementing the processor, including the accelerator, on a field-programmable gate array (FPGA), and ascertaining the possibility of realization by synthesizing using the 180 nm CMOS process.

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