Self-Replicating and Self-Repairing Multicellular Automata

1998 ◽  
Vol 4 (3) ◽  
pp. 259-282 ◽  
Author(s):  
Gianluca Tempesti ◽  
Daniel Mange ◽  
André Stauffer
Keyword(s):  
Field Programmable Gate Array ◽  
Digital Circuit ◽  
Logic Circuit ◽  
Massively Parallel ◽  
Complex Behavior ◽  
Reconfigurable Logic ◽  
Computing Systems ◽  
Field Programmable ◽  
Self Replication ◽  
Biological Organisms

Biological organisms are among the most intricate structures known to man, exhibiting highly complex behavior through the massively parallel cooperation of numerous relatively simple elements, the cells. As the development of computing systems approaches levels of complexity such that their synthesis begins to push the limits of human intelligence, engineers are starting to seek inspiration in nature for the design of computing systems, both at the software and at the hardware levels. We present one such endeavor, notably an attempt to draw inspiration from biology in the design of a novel digital circuit: a field-programmable gate array (FPGA). This reconfigurable logic circuit will be endowed with two features motivated and guided by the behavior of biological systems: self-replication and self-repair.

scholarly journals Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

2019 ◽  
Vol 29 (09) ◽  
pp. 2050136
Author(s):  
Yuuki Tanaka ◽  
Yuuki Suzuki ◽  
Shugang Wei
Keyword(s):  
Field Programmable Gate Array ◽  
High Speed ◽  
Number System ◽  
Logic Circuit ◽  
Fpga Implementation ◽  
Number Representation ◽  
Representation System ◽  
Representation Systems ◽  
Field Programmable ◽  
Gate Array

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

Field-Programmable Gate Array

2021 ◽  
pp. 257-270
Author(s):  
Mário Pereira Véstias
Keyword(s):  
Integrated Circuits ◽  
Field Programmable Gate Array ◽  
Field Programmable Gate Arrays ◽  
Software Systems ◽  
Reconfigurable Logic ◽  
Memory Cache ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Device ◽  
Programmable Gate Arrays

Field-programmable gate arrays (FPGAs) are integrated circuits whose logic and their interconnections are configurable. These devices are field-programmable, that is, they can be configured by the hardware designer without any intervention of the manufacturer. Most FPGAs can be reprogrammed as many times as we want with a vast variety of digital circuits. Some recent FPGA families are system-on-chips (SoC) with one or more microprocessor cores, memory, cache, and reconfigurable logic allowing the implementation of complex hardware/software systems in a single programmable device. This article focuses on the architecture of FPGAs, including the so called SoC FPGA. It explains the main blocks of the FPGA, how they have evolved along the last decades and the perspectives of next generation FPGAs. It also describes some applicability areas and how its architecture have evolved to adapt to some of these target markets.

MAKING A DATA ANALYSIS PROCESSOR WITH FPGA FOR GRAVITATIONAL-WAVE EVENT SEARCH

2005 ◽  
Vol 20 (29) ◽  
pp. 7057-7059
Author(s):  
NOBUAKI SATO ◽  
TOMIYOSHI HARUYAMA ◽  
TAKAKAZU SHINTOMI ◽  
TOSHIKAZU SUZUKI ◽  
TAKAYUKI TOMARU ◽  
...  
Keyword(s):  
Gravitational Wave ◽  
Field Programmable Gate Array ◽  
Fourier Transformation ◽  
Logic Circuit ◽  
Pci Bus ◽  
Fast Fourier Transformation ◽  
Wave Detector ◽  
Fft Processor ◽  
Field Programmable ◽  
Wave Event

We are trying to make a hardware logic-circuit for pipelines of fast Fourier transformation (FFT) with a field programmable gate array (FPGA) for data analyses of an interferometric gravitational-wave detector. That FFT processor is connected to a personal computer (PC) through PCI bus and will increase the calculation speed of FFT which is the most time-consuming step for typical gravitational-wave analyses.

scholarly journals A digital implementation of 2D Hindmarsh–Rose neuron

2018 ◽  
Author(s):  
Nabeeh Kandalaft ◽  
Arash Ahmadi ◽  
Moslem Heidarpur
Keyword(s):  
Neural Networks ◽  
Field Programmable Gate Array ◽  
Digital Circuit ◽  
Two Dimensional ◽  
Circuit Implementation ◽  
Digital Implementation ◽  
Signal Error ◽  
Field Programmable ◽  
Implementation Costs ◽  
Hardware Costs

Different architectures and techniques havedeveloped in the neuromorphic field to mimic andinvestigate the activity of biological neural networks.This paper presents a set of piece-wise linear approximationsof a two-dimensional Hindmarsh–Rose neuronmodel for digital circuit implementation to achievehigher speeds and lower hardware costs in large-scaleimplementation of the biological neural networks. Theperformance of the model was evaluated with a timedomain signal error. Synthesis and hardware implementationon a field-programmable gate array, as aproof of concept, indicates that the proposed modelreproduces several neuronal behaviors similar to theoriginal model with higher performance and considerablylower implementation costs.

Future Field Programmable Gate Array (FPGA) Design Methodologies and Tool Flows

2008 ◽  
Author(s):  
Michael Wirthlin ◽  
Brent Nelson ◽  
Brad Hutchings ◽  
Peter Athanas ◽  
Shawn Bohner
Keyword(s):  
Field Programmable Gate Array ◽  
Fpga Design ◽  
Design Methodologies ◽  
Field Programmable ◽  
Gate Array
Sign in / Sign up

Export Citation Format

Share Document