scholarly journals A digital implementation of 2D Hindmarsh–Rose neuron

2018 ◽  
Author(s):  
Nabeeh Kandalaft ◽  
Arash Ahmadi ◽  
Moslem Heidarpur
Keyword(s):  
Neural Networks ◽  
Field Programmable Gate Array ◽  
Digital Circuit ◽  
Two Dimensional ◽  
Circuit Implementation ◽  
Digital Implementation ◽  
Signal Error ◽  
Field Programmable ◽  
Implementation Costs ◽  
Hardware Costs

Different architectures and techniques havedeveloped in the neuromorphic field to mimic andinvestigate the activity of biological neural networks.This paper presents a set of piece-wise linear approximationsof a two-dimensional Hindmarsh–Rose neuronmodel for digital circuit implementation to achievehigher speeds and lower hardware costs in large-scaleimplementation of the biological neural networks. Theperformance of the model was evaluated with a timedomain signal error. Synthesis and hardware implementationon a field-programmable gate array, as aproof of concept, indicates that the proposed modelreproduces several neuronal behaviors similar to theoriginal model with higher performance and considerablylower implementation costs.

scholarly journals CONTROLLABLE V-SHAPE MULTISCROLL BUTTERFLY ATTRACTOR: SYSTEM AND CIRCUIT IMPLEMENTATION

2012 ◽  
Vol 22 (06) ◽  
pp. 1250143 ◽  
Author(s):  
M. AFFAN ZIDAN ◽  
A. G. RADWAN ◽  
K. N. SALAMA
Keyword(s):  
High Throughput ◽  
Field Programmable Gate Array ◽  
Small Area ◽  
Nonlinear Function ◽  
Variable Number ◽  
Experimental Results ◽  
Circuit Implementation ◽  
Digital Implementation ◽  
State Variable ◽  
Field Programmable

In this paper, a new controllable V-shape multiscroll attractor is presented, where a variety of symmetrical and unsymmetrical attractors with a variable number of scrolls can be controlled using new staircase nonlinear function and the parameters of the system. This attractor can be used to generate random signals with a variety of symbol distribution. Digital implementation of the proposed generator is also presented using a Xilinx Virtex® 4 Field Programmable Gate Array and experimental results are provided. The digital realization easily fits into a small area (<1.5% of the total area) and expresses a high throughput (4.3 Gbit/sec per state variable).

FPGA Implementation of a Soft Sensor for the Estimation of the Freezing Point of Kerosene

2009 ◽  
Author(s):  
Riccardo Caponetto ◽  
Giovanni Dongola ◽  
Antonio Gallo ◽  
Maria Gabriella Xibilia
Keyword(s):  
Neural Networks ◽  
Field Programmable Gate Array ◽  
Freezing Point ◽  
Industrial Process ◽  
Soft Sensor ◽  
Fpga Implementation ◽  
Distillation Unit ◽  
Atmospheric Distillation ◽  
New Strategy ◽  
Field Programmable

A new strategy to realize an FPGA implementation of a soft sensor for an industrial process is proposed. The proposed approach is based on the integration on Field Programmable Gate Array (FPGA) of a neural networks. The proposed method has been applied to develop a soft sensor for the estimation of the freezing point of kerosene in an atmospheric distillation unit (topping) working in a refinery in Sicily, Italy.

A Real-Time Deep Learning OFDM Receiver

2022 ◽  
Vol 15 (3) ◽  
pp. 1-25
Author(s):  
Stefan Brennsteiner ◽  
Tughrul Arslan ◽  
John Thompson ◽  
Andrew McCormick
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Real Time ◽  
Field Programmable Gate Array ◽  
Orthogonal Frequency Division Multiplexing ◽  
Frequency Division Multiplexing ◽  
Frequency Division ◽  
Field Programmable ◽  
Gate Array ◽  
Fully Connected

Machine learning in the physical layer of communication systems holds the potential to improve performance and simplify design methodology. Many algorithms have been proposed; however, the model complexity is often unfeasible for real-time deployment. The real-time processing capability of these systems has not been proven yet. In this work, we propose a novel, less complex, fully connected neural network to perform channel estimation and signal detection in an orthogonal frequency division multiplexing system. The memory requirement, which is often the bottleneck for fully connected neural networks, is reduced by ≈ 27 times by applying known compression techniques in a three-step training process. Extensive experiments were performed for pruning and quantizing the weights of the neural network detector. Additionally, Huffman encoding was used on the weights to further reduce memory requirements. Based on this approach, we propose the first field-programmable gate array based, real-time capable neural network accelerator, specifically designed to accelerate the orthogonal frequency division multiplexing detector workload. The accelerator is synthesized for a Xilinx RFSoC field-programmable gate array, uses small-batch processing to increase throughput, efficiently supports branching neural networks, and implements superscalar Huffman decoders.

scholarly journals InSight: An FPGA-Based Neuromorphic Computing System for Deep Neural Networks

2020 ◽  
Vol 10 (4) ◽  
pp. 36
Author(s):  
Taeyang Hong ◽  
Yongshin Kang ◽  
Jaeyong Chung
Keyword(s):  
Neural Networks ◽  
Image Classification ◽  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
Deep Neural Networks ◽  
Computing System ◽  
Neuromorphic Computing ◽  
Neuromorphic Hardware ◽  
Field Programmable ◽  
Gate Array

Deep neural networks have demonstrated impressive results in various cognitive tasks such as object detection and image classification. This paper describes a neuromorphic computing system that is designed from the ground up for energy-efficient evaluation of deep neural networks. The computing system consists of a non-conventional compiler, a neuromorphic hardware architecture, and a space-efficient microarchitecture that leverages existing integrated circuit design methodologies. The compiler takes a trained, feedforward network as input, compresses the weights linearly, and generates a time delay neural network reducing the number of connections significantly. The connections and units in the simplified network are mapped to silicon synapses and neurons. We demonstrate an implementation of the neuromorphic computing system based on a field-programmable gate array that performs image classification on the hand-wirtten 0 to 9 digits MNIST dataset with 99.37% accuracy consuming only 93uJ per image. For image classification on the colour images in 10 classes CIFAR-10 dataset, it achieves 83.43% accuracy at more than 11× higher energy-efficiency compared to a recent field-programmable gate array (FPGA)-based accelerator.

Self-Replicating and Self-Repairing Multicellular Automata

1998 ◽  
Vol 4 (3) ◽  
pp. 259-282 ◽  
Author(s):  
Gianluca Tempesti ◽  
Daniel Mange ◽  
André Stauffer
Keyword(s):  
Field Programmable Gate Array ◽  
Digital Circuit ◽  
Logic Circuit ◽  
Massively Parallel ◽  
Complex Behavior ◽  
Reconfigurable Logic ◽  
Computing Systems ◽  
Field Programmable ◽  
Self Replication ◽  
Biological Organisms

Biological organisms are among the most intricate structures known to man, exhibiting highly complex behavior through the massively parallel cooperation of numerous relatively simple elements, the cells. As the development of computing systems approaches levels of complexity such that their synthesis begins to push the limits of human intelligence, engineers are starting to seek inspiration in nature for the design of computing systems, both at the software and at the hardware levels. We present one such endeavor, notably an attempt to draw inspiration from biology in the design of a novel digital circuit: a field-programmable gate array (FPGA). This reconfigurable logic circuit will be endowed with two features motivated and guided by the behavior of biological systems: self-replication and self-repair.

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