Low Noise and Fast Locking Phase Locked Loop Using a Variable Delay Element in the Phase Frequency Detector

2014 ◽  
Vol 10 (1) ◽  
pp. 53-57 ◽  
Author(s):  
Umakanta Nanda ◽  
Debiprasad Priyabrata Acharya ◽  
Sarat Kumar Patra
Keyword(s):  
Phase Locked Loop ◽  
Low Noise ◽  
Variable Delay ◽  
Delay Element ◽  
Phase Frequency Detector ◽  
Frequency Detector

Analysis and Design of High Performance Phase Frequency Detector, Charge Pump and Loop Filter Circuits for Phase Locked Loop in Wireless Applications

2016 ◽  
Vol 4 (2) ◽  
pp. 397
Author(s):  
P.N. Metange ◽  
K. B. Khanchandani
Keyword(s):  
Leakage Current ◽  
High Performance ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Loop Filter ◽  
Phase Frequency Detector ◽  
Analysis And Design ◽  
Wireless Applications ◽  
5 Ghz ◽  
Frequency Detector

<p>This paper presents the analysis and design of high performance phase frequency detector, charge pump and loop filter circuits for phase locked loop in wireless applications. The proposed phase frequency detector (PFD) consumes only 8 µW and utilises small area. Also, at 1.8V voltage supply the maximum operation frequency of the conventional PFD is 500 MHz whereas proposed PFD is 5 GHz. Hence, highly suitable for low power, high speed and low jitter applications.  The differential charge pump uses switches using NMOS and the inverter delays for up and down signals do not generate any offset due to its fully symmetric operation. This configuration doubles the range of output voltage compliance compared to single ended charge pump. Differential stage is less sensitive to the leakage current since leakage current behaves as common mode offset with the dual output stages. All the circuits are implemented using cadence 0.18 μm CMOS Process.</p>

Design of improved CMOS phase-frequency detector and charge-pump for phase-locked loop

2014 ◽  
Vol 35 (10) ◽  
pp. 105006 ◽  
Author(s):  
Faen Liu ◽  
Zhigong Wang ◽  
Zhiqun Li ◽  
Qin Li ◽  
Sheng Chen
Keyword(s):  
Charge Pump ◽  
Phase Locked Loop ◽  
Phase Frequency Detector ◽  
Frequency Detector

Efficient techniques of fractional-N PLL for pervasive wireless applications

2022 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Azeem Mohammed Abdul ◽  
Usha Rani Nelakuditi
Keyword(s):  
Phase Noise ◽  
Low Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Phase Locked Loop ◽  
Oxide Semiconductor ◽  
Wireless Devices ◽  
Phase Frequency Detector ◽  
Content Type ◽  
Wireless Applications ◽  
Frequency Detector

Purpose The purpose of this paper to ensure the rapid developments in the radio frequency wireless technology, the synthesis of frequencies for pervasive wireless applications is crucial by implementing the design of low voltage and low power Fractional-N phase locked loop (PLL) for controlling medical devices to monitor remotely patients. Design/methodology/approach The developments urge a technique reliable to phase noise in designing fractional-N PLL with a new eight transistor phase frequency detector and a good linearized charge pump (CP) for speed of operation with minimum mismatches. Findings In applications for portable wireless devices, by proposing a new phase-frequency detector with the removal of dead, blind zones and a modified CP to minimize the mismatch of currents. Originality/value The results are simulated in 45 nm complementary metal oxide semiconductor generic process design kit (GPDK) technology in cadence virtuoso. The phase noise of the proposed Fractiona-N phase locked loop has–93.18, –101.4 and –117 dBc/Hz at 10 kHz, 100 kHz and 1 MHz frequency offsets, respectively, and consumes 3.3 mW from a 0.45 V supply.

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