Optimized Charge Pump and Nonlinear Phase Frequency Detector for a Ka-Band Phase-Locked Loop in 90-nm CMOS Process

2019 ◽  
Vol E102.C (11) ◽  
pp. 825-832
Author(s):  
Lu TANG ◽  
Zhigong WANG ◽  
Tiantian FAN ◽  
Faen LIU ◽  
Changchun ZHANG
Keyword(s):  
Charge Pump ◽  
Phase Locked Loop ◽  
Cmos Process ◽  
Ka Band ◽  
Phase Frequency Detector ◽  
Nonlinear Phase ◽  
Frequency Detector

Analysis and Design of High Performance Phase Frequency Detector, Charge Pump and Loop Filter Circuits for Phase Locked Loop in Wireless Applications

2016 ◽  
Vol 4 (2) ◽  
pp. 397
Author(s):  
P.N. Metange ◽  
K. B. Khanchandani
Keyword(s):  
Leakage Current ◽  
High Performance ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Loop Filter ◽  
Phase Frequency Detector ◽  
Analysis And Design ◽  
Wireless Applications ◽  
5 Ghz ◽  
Frequency Detector

<p>This paper presents the analysis and design of high performance phase frequency detector, charge pump and loop filter circuits for phase locked loop in wireless applications. The proposed phase frequency detector (PFD) consumes only 8 µW and utilises small area. Also, at 1.8V voltage supply the maximum operation frequency of the conventional PFD is 500 MHz whereas proposed PFD is 5 GHz. Hence, highly suitable for low power, high speed and low jitter applications.  The differential charge pump uses switches using NMOS and the inverter delays for up and down signals do not generate any offset due to its fully symmetric operation. This configuration doubles the range of output voltage compliance compared to single ended charge pump. Differential stage is less sensitive to the leakage current since leakage current behaves as common mode offset with the dual output stages. All the circuits are implemented using cadence 0.18 μm CMOS Process.</p>

Design of improved CMOS phase-frequency detector and charge-pump for phase-locked loop

2014 ◽  
Vol 35 (10) ◽  
pp. 105006 ◽  
Author(s):  
Faen Liu ◽  
Zhigong Wang ◽  
Zhiqun Li ◽  
Qin Li ◽  
Sheng Chen
Keyword(s):  
Charge Pump ◽  
Phase Locked Loop ◽  
Phase Frequency Detector ◽  
Frequency Detector

A LOW-VOLTAGE LOW-POWER CMOS PHASE-LOCKED LOOP

2005 ◽  
Vol 14 (05) ◽  
pp. 997-1006 ◽  
Author(s):  
ROBERT C. CHANG ◽  
LUNG-CHIH KUO ◽  
HOU-MING CHEN
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Loop Filter ◽  
Phase Frequency Detector ◽  
Low Power Cmos ◽  
Charge Pump Circuit ◽  
Frequency Detector

A low-voltage low-power CMOS phase-locked loop (PLL) is presented in this paper. It consists of a phase frequency detector, a charge pump, a loop filter, a voltage-control oscillator, and a frequency divider. A new phase frequency detector is proposed to reduce the dead zone and the mismatch effect of the charge pump circuit. A novel charge pump circuit with a small area and wide output range is described. The PLL circuit has been designed using the TSMC 0.35 μm 1P4M CMOS technology. The chip area is 1.08 mm × 1.01 mm. The post-layout simulation results show that the frequency of 900 MHz can be generated with a single supply voltage of 1.5 V. The power dissipation of the circuit is 9.17 mW.

Design and analysis of a low noise CMOS charge pump phase locked loop circuit

2021 ◽  
pp. 2140002
Author(s):  
Yanbo Chen ◽  
Shubin Zhang
Keyword(s):  
Phase Noise ◽  
Supply Voltage ◽  
Charge Pump ◽  
Phase Locked Loop ◽  
Low Noise ◽  
Cmos Process ◽  
Voltage Controlled Oscillator ◽  
Output Frequency ◽  
Power Supply Voltage ◽  
Supply Noise

Phase Locked Loop (PLL) circuit plays an important part in electronic communication system in providing high-frequency clock, recovering the clock from data signal and so on. The performance of PLL affects the whole system. As the frequency of PLL increases, designing a PLL circuit with lower jitter and phase noise becomes a big challenge. To suppress the phase noise, the optimization of Voltage Controlled Oscillator (VCO) is very important. As the power supply voltage degrades, the VCO becomes more sensitive to supply noise. In this work, a three-stage feedforward ring VCO (FRVCO) is designed and analyzed to increase the output frequency. A novel supply-noise sensing (SNS) circuit is proposed to suppress the supply noise’s influence on output frequency. Based on these, a 1.2 V 2 GHz PLL circuit is implemented in 110 nm CMOS process. The phase noise of this CMOS charge pump (CP) PLL is 117 dBc/Hz@1 MHz from test results which proves it works successfully in suppressing phase noise.

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