scholarly journals FPGA-embedded Linearized Bregman Iteration algorithm for trend break detection

2020 ◽  
Vol 2020 (1) ◽  
Author(s):  
Felipe Calliari ◽  
Gustavo Castro do Amaral ◽  
Michael Lunglmayr
Keyword(s):  
Low Complexity ◽  
Gain Factor ◽  
Iteration Algorithm ◽  
Computationally Efficient ◽  
Bregman Iteration ◽  
Sparse Estimation ◽  
Research Fields ◽  
Field Programmable ◽  
Level Shifts ◽  
Linearized Bregman Iteration

Abstract Detection of level shifts in a noisy signal, or trend break detection, is a problem that appears in several research fields, from biophysics to optics and economics. Although many algorithms have been developed to deal with such a problem, accurate and low-complexity trend break detection is still an active topic of research. The Linearized Bregman Iterations have been recently presented as a low-complexity and computationally efficient algorithm to tackle this problem, with a formidable structure that could benefit immensely from hardware implementation. In this work, a hardware architecture of the Linearized Bregman Iteration algorithm is presented and tested on a Field Programmable Gate Array (FPGA). The hardware is synthesized in different-sized FPGAs, and the percentage of used hardware, as well as the maximum frequency enabled by the design, indicate that an approximately 100 gain factor in processing time, concerning the software implementation, can be achieved. This represents a tremendous advantage in using a dedicated unit for trend break detection applications. The proposed architecture is compared with a state-of-the-art hardware structure for sparse estimation, and the results indicate that its performance concerning trend break detection is much more pronounced while, at the same time, being the indicated solution for long datasets.

Two-dimensional multiradar ISAR fusion imaging based on fast linearized Bregman iteration algorithm

2021 ◽  
Vol 15 (02) ◽  
Author(s):  
Xiaoxiu Zhu ◽  
Limin Liu ◽  
Baofeng Guo ◽  
Wenhua Hu ◽  
Lin Shi ◽  
...  
Keyword(s):  
Fusion Imaging ◽  
Iteration Algorithm ◽  
Two Dimensional ◽  
Bregman Iteration ◽  
Linearized Bregman Iteration

scholarly journals Application of Generalized Split Linearized Bregman Iteration algorithm for Alzheimer's disease prediction

Aging ◽  
2020 ◽  
Vol 12 (7) ◽  
pp. 6206-6224 ◽  
Author(s):  
Weimin Zheng ◽  
Bin Cui ◽  
Zeyu Sun ◽  
Xiuli Li ◽  
Xu Han ◽  
...  
Keyword(s):  
Alzheimer’S Disease ◽  
Alzheimer's Disease ◽  
Iteration Algorithm ◽  
Disease Prediction ◽  
Bregman Iteration ◽  
Linearized Bregman Iteration

Implementation of Biologically Inspired Components in Embedded Vision Systems

2012 ◽  
pp. 307-345 ◽  
Author(s):  
Christopher Wing Hong Ngau ◽  
Li-Minn Ang ◽  
Kah Phooi Seng
Keyword(s):  
Field Programmable Gate Array ◽  
Resource Constraints ◽  
Low Complexity ◽  
Primary Concern ◽  
Complex Data ◽  
Biologically Inspired ◽  
Computational Speed ◽  
Visual Tasks ◽  
Field Programmable ◽  
Memory Resources

Studies in the area of computational vision have shown the capability of visual attention (VA) processing in aiding various visual tasks by providing a means for simplifying complex data handling and supporting action decisions using readily available low-level features. Due to the inclusion of computational biological vision components to mimic the mechanism of the human visual system, VA processing is computationally complex with heavy memory requirements and is often found implemented in workstations with unapplied resource constraints. In embedded systems, the computational capacity and memory resources are of a primary concern. To allow VA processing in such systems, the chapter presents a low complexity, low memory VA model based on an established mainstream VA model that addresses critical factors in terms of algorithm complexity, memory requirements, computational speed, and salience prediction performance to ensure the reliability of the VA processing in an environment with limited resources. Lastly, a custom softcore microprocessor-based hardware implementation on a Field-Programmable Gate Array (FPGA) is used to verify the implementation feasibility of the presented low complexity, low memory VA model.

Biologically Inspired Components in Embedded Vision Systems

2018 ◽  
pp. 458-493
Author(s):  
Li-Minn Ang ◽  
Kah Phooi Seng ◽  
Christopher Wing Hong Ngau
Keyword(s):  
Vision System ◽  
Low Complexity ◽  
Human Vision ◽  
Primary Concern ◽  
Resource Constrained ◽  
Vision Systems ◽  
Biologically Inspired ◽  
Embedded Vision ◽  
Field Programmable ◽  
Embedded Vision Systems

Biological vision components like visual attention (VA) algorithms aim to mimic the mechanism of the human vision system. Often VA algorithms are complex and require high computational and memory requirements to be realized. In biologically-inspired vision and embedded systems, the computational capacity and memory resources are of a primary concern. This paper presents a discussion for implementing VA algorithms in embedded vision systems in a resource constrained environment. The authors survey various types of VA algorithms and identify potential techniques which can be implemented in embedded vision systems. Then, they propose a low complexity and low memory VA model based on a well-established mainstream VA model. The proposed model addresses critical factors in terms of algorithm complexity, memory requirements, computational speed, and salience prediction performance to ensure the reliability of the VA in a resource constrained environment. Finally a custom softcore microprocessor-based hardware implementation on a Field-Programmable Gate Array (FPGA) is used to verify the implementation feasibility of the presented model.

Low-Complexity MIMO MMSE Receiver with Performance Enhancement via Coordinate Interleaving

2020 ◽  
Vol 29 (14) ◽  
pp. 2050231
Author(s):  
Serdar Özyurt ◽  
Mustafa Öztürk ◽  
Enver Çavuş
Keyword(s):  
Performance Enhancement ◽  
Minimum Mean Square Error ◽  
Multiple Input Multiple Output ◽  
Low Complexity ◽  
Complexity Reduction ◽  
Error Performance ◽  
Signal Space Diversity ◽  
Mmse Receiver ◽  
Field Programmable ◽  
Input Multiple Output

Multiple-input multiple-output (MIMO) Minimum mean-square error (MMSE) receivers are widely adopted in the latest communication standards and reducing the complexity of these receivers while preserving the error performance is highly desirable. In this work, we study the error performance and implementation complexity of MIMO MMSE receivers when combined with a coordinate interleaved signal space diversity (SSD) technique. Contrary to the well-known trade-off between the error performance and implementation complexity, the proposed system leads to a considerably simplified MIMO MMSE receiver with significant performance gains when compared to the original MIMO MMSE receiver. Unlike the standard MIMO MMSE receiver, the proposed coordinate interleaved technique induces a block diagonal transmit correlation matrix providing both performance enhancement and complexity reduction. The results show that the error performance can be improved more than 10[Formula: see text]dB with up to 71% computational complexity reduction. The complexity comparison between the original and proposed approaches is also verified by means of field-programmable gate array (FPGA) implementation.

Low-Complexity Nonlinear Self-Inverse Permutation for Creating Physically Clone-Resistant Identities

Cryptography ◽  
2020 ◽  
Vol 4 (1) ◽  
pp. 6 ◽  
Author(s):  
Saleh Mulhem ◽  
Ayoub Mars ◽  
Wael Adi
Keyword(s):  
Field Programmable Gate Arrays ◽  
Low Complexity ◽  
System On Chip ◽  
Large Classes ◽  
Physical Unclonable Functions ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Security Levels ◽  
On Chip

New large classes of permutations over ℤ 2 n based on T-Functions as Self-Inverting Permutation Functions (SIPFs) are presented. The presented classes exhibit negligible or low complexity when implemented in emerging FPGA technologies. The target use of such functions is in creating the so called Secret Unknown Ciphers (SUC) to serve as resilient Clone-Resistant structures in smart non-volatile Field Programmable Gate Arrays (FPGA) devices. SUCs concepts were proposed a decade ago as digital consistent alternatives to the conventional analog inconsistent Physical Unclonable Functions PUFs. The proposed permutation classes are designed and optimized particularly to use non-consumed Mathblock cores in programmable System-on-Chip (SoC) FPGA devices. Hardware and software complexities for realizing such structures are optimized and evaluated for a sample expected target FPGA technology. The attained security levels of the resulting SUCs are evaluated and shown to be scalable and usable even for post-quantum crypto systems.

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