DESIGN FEATURES OF MICROCIRCUITS BASIC ELEMENTS FOR SPACE

2020 ◽  
Vol 13 (3) ◽  
pp. 66-70
Author(s):  
Vladimir Zolnikov ◽  
Tatyana Skvortsova ◽  
I. Strukov ◽  
Anna Ilunina ◽  
Elena Maklakova
Keyword(s):  
Cmos Technology ◽  
Signal Delay ◽  
Design Features ◽  
Matrix Crystal ◽  
Base Matrix

The article describes a microcircuit intended for certification of CMOS technology for the production of RS LSI on SPS structures. Its general and technical characteristics are considered. The description and substantiation of the construction, which unites variables by switching layers, allows to implement library elements. The library of elements of the base matrix crystal is considered: its composition and development features. Formulas for calculating the signal delay by the bistable method and estimating the duration of the front of the response of an element at its output are given.

scholarly journals Assembly technology and design features of microelectronic coordinate-sensitive detectors

2018 ◽  
pp. 21-27 ◽  
Author(s):  
V. P. Sidorenko ◽  
V. D. Zhora ◽  
O. I. Radkevich ◽  
V. P. Grunyanska ◽  
Yu. V. Prokofiev ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
High Reliability ◽  
Cmos Technology ◽  
Test Substance ◽  
Design Features ◽  
Assembly Technology ◽  
Multilayer Ceramic ◽  
A Charge ◽  
Scale Integration

The design features and assembly technology of microelectronic coordinate-sensitive detectors of charged particles for spectroscopy are considered. The device is based on the specialized very-large-scale integration (VLSI) crystal manufactured using CMOS technology and containing a charge-sensitive matrix designed to detect isotope ions in a wide mass spectrum of the test substance. The range of concentrations measured by devices is also wide and ranges from 10–7 to 100%. The VLSI crystal is placed on a multilayer ceramic basis. The devices also contain a Hamamatsu micro-channel plate (MCP), electrodes that supply high voltage to integrated circuits (2.0 kV), a non-magnetic metal shield for protecting the device components, a connector and other structural elements. VLSI crystals are installed using the method of laying the microcircuits on a flexible aluminum — polyimide media. Such mounting method has a number of advantages over others. The VLSI crystals with project standards of 1 µm are designed for the possibility to create new generation of detectors, which can include either one or several crystals. The prototype version has been developed and it allows placing a bar of five ceramic-based crystals with a minimum gap of 100 µm between them. This design provides high reliability of products due to the usage of multilayer ceramic boards and due to progressive assembly methods used in the manufacturing of special-purpose microelectronic equipment, including the equipment resistant to special external factors.

Mobility Enhancement by Strained Nitride Liners for 65nm CMOS Logic Design Features

2006 ◽  
Vol 913 ◽  
Author(s):  
Claude Ortolland ◽  
Pierre Morin ◽  
Franck Arnaud ◽  
Stephane Orain ◽  
Chandra Reddy ◽  
...  
Keyword(s):  
State Of The Art ◽  
Cmos Technology ◽  
Device Performance ◽  
Logic Design ◽  
Design Features ◽  
Induced Stress ◽  
Etch Stop ◽  
The Right ◽  
The Impact

AbstractIn this paper the impact of processed-induced stress and transistor layout on device performance in state-of-the-art 65nm CMOS technology has been studied. We have focused this analysis on different nitride liners above devices (Contact Etch-Stop Layers – CESL) which have been fabricated on two differently oriented (100) substrates: <110> and <100>. This overview permits to have a good understanding of CESL, and to choose the right strategy in terms of process induced stress in future microelectronic technologies.

A 32-Gb/s On-Chip Bus With Driver Pre-Emphasis Signaling

2009 ◽  
Vol 17 (9) ◽  
pp. 1267-1274 ◽  
Author(s):  
Liang Zhang ◽  
John M. Wilson ◽  
Rizwan Bashirullah ◽  
Lei Luo ◽  
Jian Xu ◽  
...  
Keyword(s):  
Power Dissipation ◽  
Complementary Metal Oxide Semiconductor ◽  
Current Mode ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Signal Delay ◽  
Crosstalk Noise ◽  
High Data ◽  
On Chip ◽  
Bus Architecture

This paper describes a differential current-mode bus architecture based on driver pre-emphasis for on-chip global interconnects that achieves high-data rates while reducing bus power dissipation and improving signal delay latency. The 16-b bus core fabricated in 0.25-mum complementary metal-oxide-semiconductor (CMOS) technology attains an aggregate signaling data rate of 32 Gb/s over 5-10-mm-long lossy interconnects. With a supply of 2.5 V, 25.5-48.7-mW power dissipation was measured for signal activity above 0.1, equivalent to 0.80-1.52 pJ/b. This work demonstrates a 15.0%-67.5% power reduction over a conventional single-ended voltage-mode static bus while reducing delay latency by 28.3% and peak current by 70%. The proposed bus architecture is robust against crosstalk noise and occupies comparable routing area to a reference static bus design.

scholarly journals Analysis of the results of designing reading electronics of silicon photomultiplier tubes driven by the base matrix crystal MN2XA030

Doklady BGUIR ◽  
2020 ◽  
Vol 18 (3) ◽  
pp. 81-87
Author(s):  
O. V. Dvornikov ◽  
V. A. Tchekhovski ◽  
Ya. D. Galkin ◽  
A. V. Kunts ◽  
V. R. Stempitski ◽  
...  
Keyword(s):  
Photomultiplier Tubes ◽  
Silicon Photomultiplier ◽  
Matrix Crystal ◽  
Base Matrix

scholarly journals ON DESIGN OF SELF-TUNING ACTIVE FILTERS

2020 ◽  
Vol 19 (1) ◽  
pp. 059
Author(s):  
Darko Mitić ◽  
Goran Jovanović ◽  
Mile Stojčev ◽  
Dragan Antić
Keyword(s):  
Full Range ◽  
Cmos Technology ◽  
Phase Control ◽  
Active Filters ◽  
Frequency Regulation ◽  
Pass Band ◽  
Signal Delay ◽  
Active Components ◽  
Control Loops ◽  
Self Tuning

In this paper, we present one approach in design of self-tuning all-pass, band-pass, low-pass and notch filters based on phase control loops with voltage-controlled active components and analyze their stability as well. The main idea is to vary signal delay of the filter and in this way to achieve phase correction. The filter phase characteristics are tuned by varying the transconductance of the operational transconductance amplifier or capacitance of an MOS varicap element, which are the constituents of filters. This approach allows us to implement active filters with capacitance values of order of pF, making the complete filter circuit to be amenable for realization in CMOS technology. The phase control loops are characterized by good controllable delay over the full range of phase and frequency regulation, high stability, and short settling (locking) time. The proposed circuits are suitable for implementation as a basic building RF function block, used in phase and frequency regulation, frequency synthesis, clock generation recovery, filtering, selective amplifying etc.

CMOS TECHNOLOGY FOR CCD VIDEO MEMORIES

1988 ◽  
Vol 49 (C4) ◽  
pp. C4-41-C4-44
Author(s):  
G. J.T. DAVIDS ◽  
P. B. HARTOG ◽  
J. W. SLOTBOOM ◽  
G. STREUTKER ◽  
A. G. van der SIJDE ◽  
...  
Keyword(s):  
Cmos Technology
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