Development of a trench depth measurement system for VLSI dynamic random access memory vertical capacitor cells using an interferometric technique with a Michelson interferometer

1989 ◽  
Vol 28 (16) ◽  
pp. 3373 ◽  
Author(s):  
Kazumasa Takada ◽  
Kazunori Chida ◽  
Juichi Noda ◽  
Shigeru Nakajima
2013 ◽  
Vol 25 (10) ◽  
pp. 2699-2704
Author(s):  
姚志斌 Yao Zhibin ◽  
罗尹虹 Luo Yihong ◽  
陈伟 Chen Wei ◽  
何宝平 He Baoping ◽  
张凤祁 Zhang Fengqi ◽  
...  

Author(s):  
Zongliang Huo ◽  
Seungjae Baik ◽  
Shieun Kim ◽  
In-seok Yeo ◽  
U-in Chung ◽  
...  

2021 ◽  
Vol 21 (8) ◽  
pp. 4216-4222
Author(s):  
Songyi Yoo ◽  
In-Man Kang ◽  
Sung-Jae Cho ◽  
Wookyung Sun ◽  
Hyungsoon Shin

A capacitorless one-transistor dynamic random-access memory cell with a polysilicon body (poly-Si 1T-DRAM) has a cost-effective fabrication process and allows a three-dimensional stacked architecture that increases the integration density of memory cells. Also, since this device uses grain boundaries (GBs) as a storage region, it can be operated as a memory cell even in a thin body device. GBs are important to the memory characteristics of poly-Si 1T-DRAM because the amount of trapped charge in the GBs determines the memory’s data state. In this paper, we report on a statistical analysis of the memory characteristics of poly-Si 1T-DRAM cells according to the number and location of GBs using TCAD simulation. As the number of GBs increases, the sensing margin and retention time of memory cells deteriorate due to increasing trapped electron charge. Also, “0” state current increases and memory performance degrades in cells where all GBs are adjacent to the source or drain junction side in a strong electric field. These results mean that in poly-Si 1T-DRAM design, the number and location of GBs in a channel should be considered for optimal memory performance.


2004 ◽  
Vol 43 (5A) ◽  
pp. 2457-2461 ◽  
Author(s):  
Yoshikazu Tsunemine ◽  
Tomonori Okudaira ◽  
Keiichiro Kashihara ◽  
Akie Yutani ◽  
Hiroki Shinkawata ◽  
...  

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