Purpose
The purpose of this study is to discuss the effect of hybrid cascode compensation with quality factor (Q-factor) control module for the three-stage amplifiers driving ultra-large load capacitors. Compared to the present frequency compensation solutions, it extends the amplifier bandwidth by establishing an extra AC feedback pathway besides the primary pathway through the Miller capacitor, increasing the loop gain at the gain–bandwidth product (GBW) frequency by pushing to the higher frequencies the nondominant poles.
Design/methodology/approach
A Q-factor control block is used to improve the damping factor of the compensation loop with no power or area overhead, thereby reducing the frequency peaking and the undesired oscillation in the time response for small load capacitors. The Q-factor control module is realized by a tiny-size on-chip capacitor, and provides an extra feedback loop to feed the damping current back to the input stage. A left-half-plane (LHP) zero is also introduced to further improve the stability.
Findings
A prototype of the proposed amplifier is simulated in 180-nm CMOS with a quiescent current of 24-µA from 1.80-V voltage supply. It achieves a 3.98-MHz gain–bandwidth product for 500-pF load capacitor, while the overall compensation capacitor is limited to 0.5-pF and the DC gain is extended beyond 100-dB.
Originality/value
The proposed amplifier is absolutely stable for the load capacitors ranging between 80-pF and 100-nF.
Based on time-domain quality factor (Q-factor) measurement principle, we have proposed an architecture which has the potential to be integrated on-chip. Thanks to the proposed original reconfigurable structure, the main measurement error from the offset of the operational transconductance amplifier (OTA) used can be cancelled automatically during the measurement operation, leading to a high accuracy Q-factor measurement. The digital control circuit plays an important role in the automatic passage between the two configurations designed, i.e., peak detector and comparator. The main advantages of the proposed time-domain Q-factor measurement lay on the possibility of being integrated next to the Micro Electro Mechanical System (MEMS) resonator to be measured, the miniaturization of the whole measuring system as well as the enhancement of the measurement performance, and to guide the design of such architecture, a theoretical analysis linking the required accuracy and the given Q-factor to the circuit parameters have been given in this paper. The proposed circuit is designed and simulated in a 0.35[Formula: see text][Formula: see text]m Complementary Metal Oxide Semiconductors (CMOS) technology. The post-layout simulation results show that the operating frequency can reach up to 200[Formula: see text]kHz with an accuracy of 0.4%.
This paper presents a circuit for realising a fuse-programmable capacitor on-chip. The trimming mechanism is implemented using integrated circuit fuses which can be blown in order to lower the resulting equivalent capacitance. However, for integrated circuits, the non-zero fuse resistance for active fuses and finite fuse resistance for blown fuses limit the Q factor of the resulting capacitor. In this work, we present a method on how to arrange the fuses in order to achieve maximal worst-case Q factor for the given circuit topology given the process parameters and requirements on capacitance. We also analyse and discuss the accuracy and limitations of the topology with regard to fuse resistance and parasitic elements such as bond pads.
On-chip Q-factor greater than 1 billion