scholarly journals Maximal Q Factor for an On-Chip, Fuse-Based Trimmable Capacitor

Electronics ◽  
2019 ◽  
Vol 8 (1) ◽  
pp. 62 ◽  
Author(s):  
Joakim Nilsson ◽  
Johan Borg ◽  
Jonny Johansson
Keyword(s):  
Integrated Circuits ◽  
Process Parameters ◽  
Integrated Circuit ◽  
Q Factor ◽  
Worst Case ◽  
Circuit Topology ◽  
Equivalent Capacitance ◽  
On Chip ◽  
Bond Pads ◽  
The Given

This paper presents a circuit for realising a fuse-programmable capacitor on-chip. The trimming mechanism is implemented using integrated circuit fuses which can be blown in order to lower the resulting equivalent capacitance. However, for integrated circuits, the non-zero fuse resistance for active fuses and finite fuse resistance for blown fuses limit the Q factor of the resulting capacitor. In this work, we present a method on how to arrange the fuses in order to achieve maximal worst-case Q factor for the given circuit topology given the process parameters and requirements on capacitance. We also analyse and discuss the accuracy and limitations of the topology with regard to fuse resistance and parasitic elements such as bond pads.

scholarly journals Interband Cascade Photonic Integrated Circuits on Native III-V Chip

Sensors ◽  
2021 ◽  
Vol 21 (2) ◽  
pp. 599
Author(s):  
Jerry R. Meyer ◽  
Chul Soo Kim ◽  
Mijin Kim ◽  
Chadwick L. Canedy ◽  
Charles D. Merritt ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Detection System ◽  
Laser Cavity ◽  
Building Blocks ◽  
Drive Power ◽  
Optical Elements ◽  
Photonic Integrated Circuit ◽  
Cleaved Facets ◽  
On Chip

We describe how a midwave infrared photonic integrated circuit (PIC) that combines lasers, detectors, passive waveguides, and other optical elements may be constructed on the native GaSb substrate of an interband cascade laser (ICL) structure. The active and passive building blocks may be used, for example, to fabricate an on-chip chemical detection system with a passive sensing waveguide that evanescently couples to an ambient sample gas. A variety of highly compact architectures are described, some of which incorporate both the sensing waveguide and detector into a laser cavity defined by two high-reflectivity cleaved facets. We also describe an edge-emitting laser configuration that optimizes stability by minimizing parasitic feedback from external optical elements, and which can potentially operate with lower drive power than any mid-IR laser now available. While ICL-based PICs processed on GaSb serve to illustrate the various configurations, many of the proposed concepts apply equally to quantum-cascade-laser (QCL)-based PICs processed on InP, and PICs that integrate III-V lasers and detectors on silicon. With mature processing, it should become possible to mass-produce hundreds of individual PICs on the same chip which, when singulated, will realize chemical sensing by an extremely compact and inexpensive package.

scholarly journals Organic printed photonics: From microring lasers to integrated circuits

2015 ◽  
Vol 1 (8) ◽  
pp. e1500257 ◽  
Author(s):  
Chuang Zhang ◽  
Chang-Ling Zou ◽  
Yan Zhao ◽  
Chun-Hua Dong ◽  
Cong Wei ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Flexible Electronics ◽  
Integrated Circuit ◽  
Large Scale ◽  
Rapid Development ◽  
Light Signal ◽  
Photonic Integrated Circuit ◽  
Printing Technique ◽  
On Chip ◽  
Silicon Based

A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 105, which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices.

scholarly journals Passivity Preserving Model Order Reduction Using the Reduce Norm Method

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 964
Author(s):  
Namra Akram ◽  
Mehboob Alam ◽  
Rashida Hussain ◽  
Asghar Ali ◽  
Shah Muhammad ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Model Order Reduction ◽  
High Speed ◽  
Order Reduction ◽  
Reliable Operation ◽  
Model Order ◽  
Reduced Order ◽  
Reduction Methods ◽  
On Chip

Modeling and design of on-chip interconnect, the interconnection between the components is becoming the fundamental roadblock in achieving high-speed integrated circuits. The scaling of interconnect in nanometer regime had shifted the paradime from device-dominated to interconnect-dominated design methodology. Driven by the expanding complexity of on-chip interconnects, a passivity preserving model order reduction (MOR) is essential for designing and estimating the performance for reliable operation of the integrated circuit. In this work, we developed a new frequency selective reduce norm spectral zero (RNSZ) projection method, which dynamically selects interpolation points using spectral zeros of the system. The proposed reduce-norm scheme can guarantee stability and passivity, while creating the reduced models, which are fairly accurate across selected narrow range of frequencies. The reduced order results indicate preservation of passivity and greater accuracy than the other model order reduction methods.

scholarly journals A DIRECT SEARCH METHOD FOR WORST CASE ANALYSIS AND YIELD OPTIMIZATION OF INTEGRATED CIRCUITS

2009 ◽  
Vol 18 (07) ◽  
pp. 1185-1204 ◽  
Author(s):  
GREGOR CIJAN ◽  
TADEJ TUMA ◽  
ÁRPÁD BŰRMEN
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Inequality Constraint ◽  
Direct Search ◽  
Search Method ◽  
Worst Case Analysis ◽  
Efficient Manner ◽  
Worst Case ◽  
Direct Search Method ◽  
Yield Maximization

Yield maximization is an important aspect in the design of integrated circuits. A prerequisite for its automation is a reliable and fast worst performance analysis which results in corners that can be used in the process of circuit optimization. We formulate the constrained optimization problem for finding the worst performance of an integrated circuit and develop a direct search method for solving it. The algorithm uses radial steps and rotations for enforcing the inequality constraint. We demonstrate the performance of the proposed algorithm on real world design examples of integrated circuits. The results indicate that the algorithm solves the worst performance problem in an efficient manner. The proposed algorithm was also successfully used in the process of yield maximization, resulting in a 99.65% yield.

scholarly journals Digital On-Chip Calibration of Analog Systems towards Enhanced Reliability

2021 ◽  
Author(s):  
Michal Sovcik ◽  
Lukas Nagy ◽  
Viera Stopjakova ◽  
Daniel Arbet
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Low Voltage ◽  
Supply Voltage ◽  
Electronic System ◽  
Digital Calibration ◽  
Electrical Stress ◽  
Offset Voltage ◽  
On Chip ◽  
Analog Systems

This chapter deals with digital method of calibration for analog integrated circuits as a means of extending its lifetime and reliability, which consequently affects the reliability the analog electronic system as a whole. The proposed method can compensate for drift in circuit’s electrical parameters, which occurs either in a long term due to aging and electrical stress or it is rather more acute, being caused by process, voltage and temperature variations. The chapter reveals the implementation of ultra-low voltage on-chip system of digitally calibrated variable-gain amplifier (VGA), fabricated in CMOS 130 nm technology. It operates reliably under supply voltage of 600 mV with 10% variation, in temperature range from − 20 ° C to 85 ° C . Simulations suggest that the system will preserve its parameters for at least 10 years of operation. Experimental verification over 10 packaged integrated circuit (IC) samples shows the input offset voltage of VGA is suppressed in range of 13 μV to 167 μV . With calibration the VGA closely meets its nominally designed essential specifications as voltage gain or bandwidth. Digital calibration is comprehensively compared to its widely used alternative, Chopper stabilization through its implementation for the same VGA.

Failure Analysis of Sub-Micron Semiconductor Integrated Circuit Using Backside Photon Emission Microscopy

1999 ◽  
Author(s):  
Soon Lim ◽  
Jian Hua Bi ◽  
Lian Choo Goh ◽  
Soh Ping Neo ◽  
Sudhindra Tatti
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Integrated Circuit ◽  
Flip Chip ◽  
Photon Emission ◽  
Fault Isolation ◽  
Integrated Circuit Fabrication ◽  
Circuit Fabrication ◽  
Emission Microscopy ◽  
On Chip

Abstract The progress of modern day integrated circuit fabrication technology and packaging has made fault isolation using conventional emission microscopy via the top of the integrated circuit more difficult, if not impossible. This is primarily due to the use of increased levels and density of metal-interconnect, and the advent of new packaging technology, e.g. flip-chip, ball-grid array and lead-on-chip, etc. Backside photon emission microscopy, i.e. performing photon emission microscopy through the bulk of the silicon via the back of the integrated circuit is a solution to this problem. This paper outlines the failure analysis of sub-micron silicon integrated circuits using backside photon emission microscopy. Sample preparation, practical difficulties encountered and case histories will be discussed.

Analysis of Crosstalk-Induced Effects in Multilayer Graphene Nanoribbon Interconnects

2017 ◽  
Vol 26 (06) ◽  
pp. 1750102 ◽  
Author(s):  
Manodipan Sahoo ◽  
Hafizur Rahaman
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Future Generation ◽  
Graphene Nanoribbon ◽  
Copper Interconnects ◽  
Multilayer Graphene ◽  
Crosstalk Noise ◽  
Worst Case ◽  
Suitable Alternative ◽  
The Future

Crosstalk effects in multilayer graphene nanoribbon (GNR) interconnects for the future nanoscale integrated circuits are investigated with the help of ABCD parameter matrix approach for intermediate- and global-level interconnects at 11[Formula: see text]nm and 8[Formula: see text]nm technology nodes. The worst-case crosstalk-induced delay and peak crosstalk noise voltages are derived for both neutral and doped zigzag GNR interconnects and compared to those of conventional copper interconnects. The worst-case crosstalk delays for perfectly specular, doped multilayer GNR interconnects are less than 4% of that of copper interconnects for 1[Formula: see text]mm long intermediate interconnects and less than 7% of that of copper interconnects for 5[Formula: see text]mm long global interconnects at 8[Formula: see text]nm node. As far as the worst-case peak crosstalk noise voltage is concerned, neutral GNR interconnects are slightly better performing than their doped counterparts. But from the perspective of overall noise contribution, doped GNR interconnects outperform neutral ones for all the cases. Finally, our analysis shows that from the signal integrity perspective, perfectly specular, doped multilayer zigzag GNR interconnects are a suitable alternative to copper interconnects for the future-generation integrated circuit technology.

Microfabrication of Field Emission Devices for Vacuum Integrated Circuits using Orientation Dependent Etching

1986 ◽  
Vol 76 ◽  
Author(s):  
G. J. Campisi ◽  
H. F. Gray
Keyword(s):  
Integrated Circuits ◽  
Field Emission ◽  
Integrated Circuit ◽  
High Speed ◽  
Radius Of Curvature ◽  
Hostile Environment ◽  
Electron Sources ◽  
Submicron Scale ◽  
On Chip ◽  
Extraction Electrode

ABSTRACTVacuum integrated circuits and field emission (FE) devices with geometries on the micron and submicron scale have been discussed as alternatives to solid state devices for high speed and hostile environment application as well as for miniature electron sources for CRTs. These miniaturized vacuum devices have been developed on the basis of the advances in micromachining technology, i.e. orientation-dependent etching (ODE) of lithographically patterned silicon. This paper describes the ODE methods used to fabricate pyramidal electron emitter points 1.5 μm high, with radius of curvature of 20 to 100 nm from <100> silicon. In order to reduce operating voltages, an integral extraction electrode (grid) was fabricated by a self-aligned technique. With a single gate mask level the extraction and planar collector structures were fabricated on chip, to form a planar vacuum triode. The final mask step provided the flexibility for fabricating a variety of planar vacuum integrated circuit elements.

PRACTICAL METHODS FOR WORST-CASE AND YIELD ANALYSIS OF ANALOG INTEGRATED CIRCUITS

1993 ◽  
Vol 04 (03) ◽  
pp. 261-282 ◽  
Author(s):  
KURT J. ANTREICH ◽  
HELMUT E. GRAEB ◽  
CLAUDIA U. WIESER
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Parametric Design ◽  
Case Analysis ◽  
Operating Conditions ◽  
Worst Case Analysis ◽  
Performance Limits ◽  
Integrated Circuit Design ◽  
Worst Case ◽  
Circuit Performance

Worst-case analysis is commonly used in integrated circuit design to verify a satisfactory circuit performance with regard to changes in the manufacturing conditions. However, worst-case analysis is often carried out using approximate worst-case parameter sets. This paper presents a new approach to the worst-case design of integrated circuits that takes account of fluctuations in the operating conditions. It provides exact and unique worst-case manufacturing conditions and worst-case operating conditions for given circuit specifications. These specifications may be either performance limits or minimum yield requirements. The method is illustrated with the parametric design of integrated CMOS bias stages.

Scanning Electron Microscopy in Hybrid Microelectronics

1976 ◽  
Vol 34 ◽  
pp. 456-457
Author(s):  
S. Khadpe ◽  
R. Faryniak
Keyword(s):  
Integrated Circuits ◽  
Thick Film ◽  
Integrated Circuit ◽  
Failure Modes ◽  
Three Dimensional ◽  
Circuit Components ◽  
Hybrid Microcircuit ◽  
Electrical Connections ◽  
Scanning Electron

The Scanning Electron Microscope (SEM) is an important tool in Thick Film Hybrid Microcircuits Manufacturing because of its large depth of focus and three dimensional capability. This paper discusses some of the important areas in which the SEM is used to monitor process control and component failure modes during the various stages of manufacture of a typical hybrid microcircuit.Figure 1 shows a thick film hybrid microcircuit used in a Motorola Paging Receiver. The circuit consists of thick film resistors and conductors screened and fired on a ceramic (aluminum oxide) substrate. Two integrated circuit dice are bonded to the conductors by means of conductive epoxy and electrical connections from each integrated circuit to the substrate are made by ultrasonically bonding 1 mil aluminum wires from the die pads to appropriate conductor pads on the substrate. In addition to the integrated circuits and the resistors, the circuit includes seven chip capacitors soldered onto the substrate. Some of the important considerations involved in the selection and reliability aspects of the hybrid circuit components are: (a) the quality of the substrate; (b) the surface structure of the thick film conductors; (c) the metallization characteristics of the integrated circuit; and (d) the quality of the wire bond interconnections.

Sign in / Sign up

Export Citation Format

Share Document