Low Power Considerations in Ubiquitous Computing

2010 ◽  
pp. 158-174
Author(s):  
Robert Tesch ◽  
Ashok Kumar ◽  
Jamie Mason ◽  
Dania Alvarez ◽  
Mario Di’Mattia ◽  
...  
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Ubiquitous Computing ◽  
Reducing Power ◽  
Low Power Design ◽  
Power Budget ◽  
Computing Systems ◽  
Research Directions ◽  
Design Considerations ◽  
Battery Technology

Majority of the devices that are used in ubiquitous computing are expected to be as small as possible, be able to perform as many computations as possible, and transmit the results to another device or computer. Such expectations in performance put a pressure on the power budget of such devices. It is a well-known fact that the advances in battery technology are much slower and cannot keep up with the performance demands of tiny gadgets unless new methods of designing and managing hardware and software are developed and used. This chapter will introduce the motivation for low power design considerations by discussing the power limitations of ubiquitous computing devices. Then the chapter will discuss the research directions that are being pursued in literature for reducing power consumption and increasing efficiency of ubiquitous computing systems.

scholarly journals LOW POWER DIGITAL FILTERING USING ADAPTIVE APPROXIMATE PROCESSING: FIR FILTER STRUCTURES

2021 ◽  
pp. 1-5
Author(s):  
JEFFREY LUDWIG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Digital Filter ◽  
Signal To Noise Ratio ◽  
Reducing Power ◽  
Digital Filtering ◽  
Low Power Design ◽  
Time Varying ◽  
Filtering Algorithms ◽  
Filter Structures

Techniques for reducing power consumption in digital circuits have become increasingly important because of the growing demand for portable multimedia devices. Digital filters, being ubiquitous in such devices, are a prime candidate for low power design. Algorithmic approaches to low power frequency-selective digital filtering which are based on the concepts of adaptive approximate processing have been developed and formalized by introducing the class of approximate filtering algorithms in which the order of a digital filter is dynamically varied to provide time-varying stopband attenuation in proportion to the time-varying signal-to-noise ratio (SNR) of the input signal, while maintaining a fixed SNR at the filter output. Since power consumption in digital filter implementations is proportional to the order of the filter, dynamically varying the filter order is a strategy which may be used to conserve power. In this paper we introduce a class of approximate filter structures using FIR digital filter constituent elements. These filter structures are explored and shown to be an important element in the characterization of approximate filtering algorithms.

scholarly journals The Importance of Energy Efficiency in Engineering and Informatics

2021 ◽  
Vol 2 (2) ◽  
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Digital Circuits ◽  
Reducing Power ◽  
Digital Filtering ◽  
Low Power Design ◽  
Engineering Systems ◽  
Algorithmic Approach ◽  
Modern Engineering ◽  
Power Frequency

Techniques for reducing power consumption in digital circuits that underly automatic control of modern engineering systems are of paramount importance due to the simultaneously growing demands for portable multimedia devices and energy conservation. Digital filters, being ubiquitous in such devices, are thus a prime candidate for low power design. We review an algorithmic approach to low power frequency-selective digital filtering, an essential ingredient for energy efficient technological innovation in many domains.

scholarly journals The Importance of Energy Efficiency in Engineering and Informatics

2021 ◽  
Vol 2 (2) ◽  
Keyword(s):  
Low Power ◽  
Energy Efficient ◽  
Digital Circuits ◽  
Reducing Power ◽  
Digital Filtering ◽  
Low Power Design ◽  
Engineering Systems ◽  
Algorithmic Approach ◽  
Modern Engineering ◽  
Power Frequency

Techniques for reducing power consumption in digital circuits that underly automatic control of modern engineering systems are of paramount importance due to the simultaneously growing demands for portable multimedia devices and energy conservation. Digital filters, being ubiquitous in such devices, are thus a prime candidate for low power design. We review an algorithmic approach to low power frequency-selective digital filtering, an essential ingredient for energy efficient technological innovation in many domains.

Green Semicondoctor Design Techniques and Challanges

2011 ◽  
pp. 404-411
Author(s):  
Somesh Rajain ◽  
Chetan Shingala ◽  
Ekata Mehul
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Power Management ◽  
Human Life ◽  
Semiconductor Industry ◽  
Low Power Design ◽  
Clock Gating ◽  
Consumer Device ◽  
Carbon Dioxide Co2 ◽  
Design Techniques

The large emission of Carbon dioxide (CO2) is not only affecting our ecology but also affecting human life. In schools, offices, factory and crowded railway/bus stations i.e crowded places with insufficient ventilations CO2 affects human life most. In a closed environment like school, If CO2 level starts raising above 700 parts per million (ppm) people will feel objectionable body odors and as it increase further people will feel very uncomfortable, dizzy and have headache etc. Our goal is to reduce CO2 emission and lower global warming. In Semiconductor Industry as the digital technology grows, the functionality of our electronics devices (For example: - Mobile phone, PC’s, home appliances etc) is constantly improves and mean while the demand for electronic devices to be more environment friendly is increasing. So we have to design systems with Low power consumption to curtail down green house gas emission as well as low power design are also a requirement of today’s market. The usage of mobile device in all kinds of applications is increasing day by day. These applications and corresponding devices also have their power requirements. The demand for mobile consumer device has made the power management the number one consideration in today‘s system design. To increase battery life, system chip designer needs to adopt an aggressive power management technique which includes multi voltage Design Island, power gating, dynamic voltage, frequency scaling, clock gating etc in the system. Adding all these greatly complicates the verification for the chip. Normally the designer neglects the implementation of power saving techniques due to the tradeoff between power reduction and verification costs. The costs become more important in terms of business, which leads to more power consumption. Those details can still be implemented provided we use right kind of tools & techniques that are also combined with design experience. In this chapter the focus is to firstly describe low power design techniques, its verification challenges and its solutions followed by the case study. It also guides for the selection of programmable device & RTL Core design criteria. To make green electronics devices we have to design system with low power design techniques.

scholarly journals Encoding Schemes for Reducing Transition Activity and Power Consumption in VLSI Interconnects-A Review

2018 ◽  
Vol 7 (3.1) ◽  
pp. 34
Author(s):  
Vithyalakshmi. N ◽  
Nagarajan P ◽  
Ashok Kumar.N ◽  
Vinoth. G.S
Keyword(s):  
Energy Dissipation ◽  
Power Consumption ◽  
Low Power ◽  
Vlsi Design ◽  
Low Power Design ◽  
System Size ◽  
Vlsi Circuits ◽  
Portable Devices ◽  
Dynamic Power ◽  
Transition Activity

Low power design is a foremost challenging issue in recent applications like mobile phones and portable devices. Advances in VLSI technology have enabled the realization of complicated circuits in single chip, reducing system size and power utilization. In low power VLSI design energy dissipation has to be more significant. So to minimize the power consumption of circuits various power components and their effects must be identified. Dynamic power is the major energy dissipation in micro power circuits. Bus transition activity is the major source of dynamic power consumption in low power VLSI circuits. The dynamic power of any complex circuits cannot be estimated by the simple calculations. Therefore this paper review different encoding schemes for reduction of transition activity and power dissipation. 

Design of the Improved Accompanying Temperature Logger

2014 ◽  
Vol 989-994 ◽  
pp. 3015-3018
Author(s):  
Juan Guo ◽  
Shi Ying Liang ◽  
Zong Tao Yin
Keyword(s):  
Power Consumption ◽  
Energy Conservation ◽  
Low Power ◽  
Communication Protocol ◽  
Reducing Power ◽  
Experimental Tests ◽  
Low Power Consumption ◽  
Temperature Logger ◽  
Ultra Low Power

This paper describes research on some methods of reducing power consumption to reduce the volume accompanying logger. For the requirement of ultra-low power consumption and miniature, the design is described separately from the hardware and software, mainly including temperature detecting module, interface of communication, low current circuit hardware, energy conservation ,arouse from power down state, communication protocol, etc. The experimental tests for device prove that the research can achieve low power requirements.

Research of Low Power Design Strategy Based on IEEE 1801 Unified Power Format

2014 ◽  
Vol 981 ◽  
pp. 21-24
Author(s):  
Shu Ping Cui ◽  
Chuang Xie
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Circuit Design ◽  
High Power ◽  
Low Power Design ◽  
Design Strategy ◽  
Design Flow ◽  
Battery Life ◽  
Electronic Systems ◽  
High Power Consumption

Power consumption is becoming an increasingly important aspect of circuit design. High power consumption can lead to high machine temperature, short battery life which makes laptop electronics difficult to be widely used. IEEE 1801 Unified Power Format (UPF) is designed to express power intent for electronic systems and components .This paper first introduces the power principles, puts forward the approaches to reduce power consumption according to UPF, and then demonstrates the Synopsys design flow based on UPF, finally gives the power report and makes a conclusion.

FLOORPLAN DESIGN WITH LOW POWER CONSIDERATIONS

1996 ◽  
Vol 07 (02) ◽  
pp. 305-322
Author(s):  
KAI-YUAN CHAO ◽  
D. F. WONG
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Power Design ◽  
Network Size ◽  
Total Power ◽  
Wire Length ◽  
Performance Requirements ◽  
Total Power Consumption ◽  
Distribution Of Power ◽  
The Cost

In this paper, a floorplanner for low power design is presented. Our objective is to optimize total power consumption and area during the selection and placement of various implementations for circuit modules. Furthermore, the proposed method considers performance requirements, power line noises, and distribution of power consumption in order to generate lower and evenly distributed power dissipation over the resulting circuit floorplan with a specified performance. For a set of benchmark circuits we tested, on the average, our floorplanner can achieve decreases of total power consumption, wire-length, and power/ground network size by 18.3%, 4.6%, and 24%, respectively, at the cost of an area increase of 8.8% when compared with an existing area/wire-length driven floorplanner.

A Low Power Design of SM4 Cipher Based on MUX S-Box Architecture

2013 ◽  
Vol 411-414 ◽  
pp. 125-130
Author(s):  
Yan Bo Niu ◽  
An Ping Jiang
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Data Transmission ◽  
Block Cipher ◽  
Low Power Design ◽  
Cmos Technology ◽  
Smart Cards ◽  
Low Power Consumption

SM4 is a 128-bit block cipher used in SOC and smart cards to ensure the safety of data transmission. In order to realize a low power implementation of the SM4 cipher block, some S-boxes were evaluated firstly and we proposed a new architecture of SM4 S-box called MUX S-box with a power consumption of 13.92W@10Mhz on SMIC 0.18m technology, Meanwhile, the implementation of SM4 cipher round based on the SM4 MUX S-box was completed and a low power consumption of 0.33mW @ 10 MHz on 0.18 m CMOS technology is achieved.

scholarly journals Clocking in multi-GHz environment

2002 ◽  
Vol 15 (1) ◽  
pp. 13-31
Author(s):  
Vojin Oklobdzija
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Low Power Design ◽  
Systematic Design ◽  
Time Borrowing

An overview of clocking and design of clocked storage elements is presented. Systematic design of ip-op is explained as well as "time borrowing" and absorption of clock uncertainties. We show how should different clocked storage elements be compared against each other. The issues related to power consumption and low-power design are presented.

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