scholarly journals Low power combinational and sequential logic circuits using clocked differential cascode adiabatic logic (CDCAL)

2018 ◽  
Vol 7 (3) ◽  
pp. 1548
Author(s):  
P Sasipriya ◽  
V S Kanchana Bhaaskaran
Keyword(s):  
Low Power ◽  
High Speed ◽  
Dynamic Logic ◽  
Logic Circuits ◽  
Clock Signal ◽  
Two Phase ◽  
Industry Standard ◽  
Look Ahead ◽  
Adiabatic Logic ◽  
Sequential Logic

This paper presents the Clocked Differential Cascode Adiabatic Logic (CDCAL), the quasi-adiabatic dynamic logic that can operate efficiently at GHz-class frequencies. It is operated by two phase sinusoidal power clock signal for the adiabatic pipeline. The proposed logic uses clocked control transistor in addition to the less complex differential cascode logic structure to achieve low power and high speed operation. To show the feasibility of implementation of both combinational and sequential logic circuits using the proposed logic, the CLA adder and counter have been selected. To evaluate the energy efficiency of the proposed logic, an 8-bit pipelined carry look-ahead (CLA) adder is designed using CCDAL and it is also compared against the other high speed two phase counterpart available in the literature and conventional static CMOS. The simulation results show that the CCDAL logic can operate efficiently at high frequencies compared to other two phase adiabatic logic circuits. All the circuits have been designed using UMC 90nm technology library and the simulations are carried out using industry standard Cadence® Virtuoso tool.  

Design of Low Power VLSI Circuits Using Two Phase Adiabatic Dynamic Logic (2PADL)

2017 ◽  
Vol 27 (04) ◽  
pp. 1850052 ◽  
Author(s):  
P. Sasipriya ◽  
V. S. Kanchana Bhaaskaran
Keyword(s):  
Energy Efficiency ◽  
Low Power ◽  
Energy Recovery ◽  
Dynamic Logic ◽  
Vlsi Circuits ◽  
Clock Signal ◽  
Two Phase ◽  
Look Ahead ◽  
Adiabatic Logic ◽  
Speed Performance

This paper presents the quasi-adiabatic logic for low power powered by two phase sinusoidal clock signal. The proposed logic called two phase adiabatic dynamic logic (2PADL) realizes the advantages of energy efficiency through the use of gate overdrive and reduced switching power. It has a single rail output and the proposed logic does not require the complementary input signals for any of its variables. The 2PADL logic is operated by two complementary clock signals acting as power supply. The validation of the proposed logic is carried out through practical circuits such as (i) sequential circuits using energy recovery technique suitable for memory circuits, (ii) an adiabatic carry look ahead adder (CLA) designed using 2PADL to study the speed performance and to prove its energy efficiency across a range of frequencies and (iii) a multiplier circuit using 2PADL compared against CMOS counterpart. The CLA adder is also implemented using the other static adiabatic logics, namely, quasi static energy recovery logic (QSERL), clocked CMOS adiabatic logic (CCAL) and conventional static CMOS logic to compare against 2PADL and validate its power advantages. The performance of the CCAL logic is tested for higher frequencies by implementing the widely presented CLA circuit. The result proves that the design is energy efficient and operates up to the frequency of 600 MHz. The simulation was carried out using industry standard Cadence® Virtuoso tool using 180[Formula: see text]nm technology library files.

scholarly journals Energy Efficient Digital Circuits using Two Phase Clocking Sub-Threshold Adiabatic Logic

2019 ◽  
Vol 8 (2) ◽  
pp. 101-106
Keyword(s):  
Low Power ◽  
High Speed ◽  
Digital Circuits ◽  
Vlsi Design ◽  
Logic Circuit ◽  
Oxide Semiconductor ◽  
Process Technology ◽  
Two Phase ◽  
Adiabatic Logic ◽  
On Chip

Power is a major constraint in Digital VLSI circuits, due to reduction in sizes of Metal Oxide Semiconductor (MOS) transistors are scaling down. Low-power technologies are used to diminish the power utilization be able to be classified as Sub-threshold CMOS and Adiabatic logic tachniques. In, Sub-threshold CMOS defines a system which reduces the power utilization to inferior than the threshold voltage of a MOS Device, where as Adiabatic logic circuit is a method which minimizes the energy usage through suppress the applied voltage to the resistance of a given VLSI design. This effort deals to offer a subthreshold adiabatic logic circuit of low power CMOS circuits that uses 2φ clocking subthreshold Adiabatic Logic. The digital circuits were designed in HSPICE using 0.18 μm CMOS standard process technology. It is evident from the results that the 2φ Clocking Subthreshold Adiabatic design is beneficial in major application where power starving is of major significance at the same time as in elevated its performance efficiency in DSP processor IC, System on chip, Network on chip and High speed digital ICs.

Limited switch dynamic logic circuits for high-speed low-power circuit design

2006 ◽  
Vol 50 (2.3) ◽  
pp. 277-286 ◽  
Author(s):  
W. Belluomini ◽  
D. Jamsek ◽  
A. K. Martin ◽  
C. McDowell ◽  
R. K. Montoye ◽  
...  
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
High Speed ◽  
Dynamic Logic ◽  
Logic Circuits ◽  
Power Circuit

Design of Equivalent Sampling Based on Printed Circuit Board Suited for Power Communication System

2013 ◽  
Vol 333-335 ◽  
pp. 465-471
Author(s):  
Chuan Liu ◽  
Zhi Chao Huang ◽  
Peng Wu ◽  
Lei Chen ◽  
Wei Wang
Keyword(s):  
Time Delay ◽  
Communication System ◽  
High Speed ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Transmission Time ◽  
Clock Signal ◽  
Signal Delay ◽  
Printed Circuit ◽  
Sequential Logic

Many applications in Power communication system have a demand of adjustable transmission time delay of high-speed signal. In sequential logic circuit, the control of transmission time delay of high-speed signal can effectively improve the accuracy of clock sampling, as a result, satisfy the constraints between clock signal and periodic data. A method of equivalent sampling based on printed circuit board (PCB) is provided in the article, it realizes equivalent sampling of the data by fixing a group of clock signal delay, thus, increase the accuracy of sampling.

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