Two-phase dynamic FET logic: an extremely low power, high speed logic family for GaAs VLSI

2002 ◽  
Author(s):  
K.R. Nary ◽  
S.I. Long
Keyword(s):  
Low Power ◽  
High Speed ◽  
Two Phase ◽  
Phase Dynamic

scholarly journals Energy Efficient Digital Circuits using Two Phase Clocking Sub-Threshold Adiabatic Logic

2019 ◽  
Vol 8 (2) ◽  
pp. 101-106
Keyword(s):  
Low Power ◽  
High Speed ◽  
Digital Circuits ◽  
Vlsi Design ◽  
Logic Circuit ◽  
Oxide Semiconductor ◽  
Process Technology ◽  
Two Phase ◽  
Adiabatic Logic ◽  
On Chip

Power is a major constraint in Digital VLSI circuits, due to reduction in sizes of Metal Oxide Semiconductor (MOS) transistors are scaling down. Low-power technologies are used to diminish the power utilization be able to be classified as Sub-threshold CMOS and Adiabatic logic tachniques. In, Sub-threshold CMOS defines a system which reduces the power utilization to inferior than the threshold voltage of a MOS Device, where as Adiabatic logic circuit is a method which minimizes the energy usage through suppress the applied voltage to the resistance of a given VLSI design. This effort deals to offer a subthreshold adiabatic logic circuit of low power CMOS circuits that uses 2φ clocking subthreshold Adiabatic Logic. The digital circuits were designed in HSPICE using 0.18 μm CMOS standard process technology. It is evident from the results that the 2φ Clocking Subthreshold Adiabatic design is beneficial in major application where power starving is of major significance at the same time as in elevated its performance efficiency in DSP processor IC, System on chip, Network on chip and High speed digital ICs.

scholarly journals Low power combinational and sequential logic circuits using clocked differential cascode adiabatic logic (CDCAL)

2018 ◽  
Vol 7 (3) ◽  
pp. 1548
Author(s):  
P Sasipriya ◽  
V S Kanchana Bhaaskaran
Keyword(s):  
Low Power ◽  
High Speed ◽  
Dynamic Logic ◽  
Logic Circuits ◽  
Clock Signal ◽  
Two Phase ◽  
Industry Standard ◽  
Look Ahead ◽  
Adiabatic Logic ◽  
Sequential Logic

This paper presents the Clocked Differential Cascode Adiabatic Logic (CDCAL), the quasi-adiabatic dynamic logic that can operate efficiently at GHz-class frequencies. It is operated by two phase sinusoidal power clock signal for the adiabatic pipeline. The proposed logic uses clocked control transistor in addition to the less complex differential cascode logic structure to achieve low power and high speed operation. To show the feasibility of implementation of both combinational and sequential logic circuits using the proposed logic, the CLA adder and counter have been selected. To evaluate the energy efficiency of the proposed logic, an 8-bit pipelined carry look-ahead (CLA) adder is designed using CCDAL and it is also compared against the other high speed two phase counterpart available in the literature and conventional static CMOS. The simulation results show that the CCDAL logic can operate efficiently at high frequencies compared to other two phase adiabatic logic circuits. All the circuits have been designed using UMC 90nm technology library and the simulations are carried out using industry standard Cadence® Virtuoso tool.  

HIGH SPEED AND LOW POWER 4*4 ARRAY MULTIPLIER DESIGN

2019 ◽  
Vol 7 (1) ◽  
pp. 24
Author(s):  
N. SURESH ◽  
K. S. SHAJI ◽  
KISHORE REDDY M. CHAITANYA ◽  
◽  
◽  
...  
Keyword(s):  
Low Power ◽  
High Speed ◽  
Array Multiplier

Design and Implementation of an Efficient Parallel LFSR Architecture for Wireless Communication Systems

2019 ◽  
Vol 14 ◽  
Author(s):  
A. Suresh Babu ◽  
B. Anand
Keyword(s):  
Wireless Communication ◽  
Power Consumption ◽  
Low Power ◽  
Communication Systems ◽  
High Speed ◽  
Design Tool ◽  
Shift Register ◽  
Linear Feedback ◽  
Wireless Communication Systems ◽  
Coverage Area

: A Linear Feedback Shift Register (LFSR) considers a linear function typically an XOR operation of the previous state as an input to the current state. This paper describes in detail the recent Wireless Communication Systems (WCS) and techniques related to LFSR. Cryptographic methods and reconfigurable computing are two different applications used in the proposed shift register with improved speed and decreased power consumption. Comparing with the existing individual applications, the proposed shift register obtained >15 to <=45% of decreased power consumption with 30% of reduced coverage area. Hence this proposed low power high speed LFSR design suits for various low power high speed applications, for example wireless communication. The entire design architecture is simulated and verified in VHDL language. To synthesis a standard cell library of 0.7um CMOS is used. A custom design tool has been developed for measuring the power. From the results, it is obtained that the cryptographic efficiency is improved regarding time and complexity comparing with the existing algorithms. Hence, the proposed LFSR architecture can be used for any wireless applications due to parallel processing, multiple access and cryptographic methods.

Low Power and High Speed Sequential Circuits Test Architecture

2019 ◽  
Vol 12 ◽  
Author(s):  
Ahmed K. Jameil ◽  
Yasir Amer Abbas ◽  
Saad Al-Azawi
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Test Generation ◽  
High Speed ◽  
Fir Filter ◽  
Sequential Circuits ◽  
Fir Filters ◽  
Design Verification ◽  
Sequential Circuit ◽  
Generation Algorithm

Background: The designed circuits are tested for faults detection in fabrication to determine which devices are defective. The design verification is performed to ensure that the circuit performs the required functions after manufacturing. Design verification is regarded as a test form in both sequential and combinational circuits. The analysis of sequential circuits test is more difficult than in the combinational circuit test. However, algorithms can be used to test any type of sequential circuit regardless of its composition. An important sequential circuit is the finite impulse response (FIR) filters that are widely used in digital signal processing applications. Objective: This paper presented a new design under test (DUT) algorithm for 4-and 8-tap FIR filters. Also, the FIR filter and the proposed DUT algorithm is implemented using field programmable gate arrays (FPGA). Method: The proposed test generation algorithm is implemented in VHDL using Xilinx ISE V14.5 design suite and verified by simulation. The test generation algorithm used FIR filtering redundant faults to obtain a set of target faults for DUT. The fault simulation is used in DUT to assess the benefit of test pattern in fault coverage. Results: The proposed technique provides average reductions of 20 % and 38.8 % in time delay with 57.39 % and 75 % reductions in power consumption and 28.89 % and 28.89 % slices reductions for 4- and 8-tap FIR filter, respectively compared to similar techniques. Conclusions: The results of implementation proved that a high speed and low power consumption design can be achieved. Further, the speed of the proposed architecture is faster than that of existing techniques.

Sign in / Sign up

Export Citation Format

Share Document