Design and Analysis of Low-Power Adiabatic Logic Circuits by Using CNTFET Technology

2019 ◽  
Vol 38 (9) ◽  
pp. 4338-4356
Author(s):  
Ajay Kumar Dadoria ◽  
Kavita Khare
Keyword(s):  
Low Power ◽  
Logic Circuits ◽  
Adiabatic Logic

Cascadable adiabatic logic circuits for low-power applications

2008 ◽  
Vol 2 (6) ◽  
pp. 518 ◽  
Author(s):  
N.S.S. Reddy ◽  
M. Satyam ◽  
K.L. Kishore
Keyword(s):  
Low Power ◽  
Logic Circuits ◽  
Adiabatic Logic

scholarly journals Design of Low Power Multiplexer and De-Multiplexer using Different Adiabatic Logics

2020 ◽  
Vol 9 (1) ◽  
pp. 465-473
Keyword(s):  
Low Power ◽  
Circuit Design ◽  
Power Dissipation ◽  
Digital Circuit ◽  
Logic Circuits ◽  
Digital Circuit Design ◽  
Adiabatic Logic ◽  
Low Power Dissipation ◽  
In Series ◽  
Main Factor

In this paper we proposed, design and evaluation of 16:1 Multiplexer and 1:16 Demultiplexer using different adiabatic logics. Power consumption is the main factor in VLSI digital circuit design. Here we have introduced a CMOS-logic based 16:1 Multiplexer and 1:16 De-multiplexer with a low power adiabatic logic. In which we concentrate on the characteristics of the CMOS and adiabatic logics such as 2N2P, 2N-2N2P and Dual sleep. Wherein both 2N2P and 2N2N2P use a cross-coupled transistor structure for adiabatic operation. Adiabatic logic circuits use reverse logic and the power dissipation will be less compared to the CMOS circuits as the inputs are given to the n-type functional tree in 2N2P and 2N2N2P. For dual sleep logic an additional circuit is connected in series with general CMOS circuit known as sleep circuit. we have concentrated on energy recovery and power dissipation, as all these technique results in the low power dissipation. Dualsleep is considered as the best of the all the other adiabatic and traditional logics

scholarly journals Low power combinational and sequential logic circuits using clocked differential cascode adiabatic logic (CDCAL)

2018 ◽  
Vol 7 (3) ◽  
pp. 1548
Author(s):  
P Sasipriya ◽  
V S Kanchana Bhaaskaran
Keyword(s):  
Low Power ◽  
High Speed ◽  
Dynamic Logic ◽  
Logic Circuits ◽  
Clock Signal ◽  
Two Phase ◽  
Industry Standard ◽  
Look Ahead ◽  
Adiabatic Logic ◽  
Sequential Logic

This paper presents the Clocked Differential Cascode Adiabatic Logic (CDCAL), the quasi-adiabatic dynamic logic that can operate efficiently at GHz-class frequencies. It is operated by two phase sinusoidal power clock signal for the adiabatic pipeline. The proposed logic uses clocked control transistor in addition to the less complex differential cascode logic structure to achieve low power and high speed operation. To show the feasibility of implementation of both combinational and sequential logic circuits using the proposed logic, the CLA adder and counter have been selected. To evaluate the energy efficiency of the proposed logic, an 8-bit pipelined carry look-ahead (CLA) adder is designed using CCDAL and it is also compared against the other high speed two phase counterpart available in the literature and conventional static CMOS. The simulation results show that the CCDAL logic can operate efficiently at high frequencies compared to other two phase adiabatic logic circuits. All the circuits have been designed using UMC 90nm technology library and the simulations are carried out using industry standard Cadence® Virtuoso tool.  

Sign in / Sign up

Export Citation Format

Share Document