The Mechanism of J-V “Roll-Over” in CdS/CdTe Devices

2007 ◽  
Vol 1012 ◽  
Author(s):  
Jie Zhou ◽  
Xuanzhi Wu ◽  
Yanfa Yan ◽  
Sally Asher ◽  
Juarez Da Silva ◽  
...  
Keyword(s):  
Back Side ◽  
Back Contact ◽  
Front Side ◽  
Current Voltage

AbstractThe “roll-over” phenomenon in current-voltage (J-V) curves of CdS/CdTe devices is recognized as a result of the formation of a higher back barrier. When Cu has not been intentionally added to the back contact, roll-over is understandable. However, the mechanism was unclear for forming J-V roll-over in a CdTe cell with a back contact containing Cu. We did extensive characterizations, including XRD, XPS, SIMS, TEM, and EDS, and “recontact” experiments to understand this phenomenon. The results show that the roll-over comes from the formation of Cu-related oxides at the back side of the device during processing, rather than the diffusion of Cu to the front side of the device. Discussions related to the J-V roll-over mechanisms will also be presented.

A Novel Silicon Base Piezoresistive Pressure Sensor Using Front Side Etching Process

2003 ◽  
Author(s):  
Chih-Tang Peng ◽  
Ji-Cheng Lin ◽  
Chun-Te Lin ◽  
Kuo-Ning Chiang ◽  
Jin-Shown Shie
Keyword(s):  
Pressure Sensor ◽  
Thermal Loading ◽  
Fabrication Process ◽  
Back Side ◽  
The Novel ◽  
Front Side ◽  
Sensor Performance ◽  
Novel Structure ◽  
Piezoresistive Pressure Sensor ◽  
Packaging Structure

By applying the etching via technology, this study proposes a novel front-side etching fabrication process for a silicon based piezoresistive pressure sensor to replace the conventional backside bulk micro-machining. The distinguishing features of this novel structure are chip size reduction and fabrication costs degradation. In order to investigate the sensor performance and the sensor packaging effect of the structure proposed in this research, the finite element method was adopted for analyzing the sensor sensitivity and stability. The sensitivity and the stability of the novel sensor after packaging were studied by applying mechanical as well as thermal loading to the sensor. Furthermore, the fabrication process and the sensor performance of the novel pressure sensor were compared with the conventional back-side etching type pressure sensor for the feasibility validation of the novel sensor. The results showed that the novel pressure sensor provides better sensitivity than the conventional one, and the sensor output signal stability can be enhanced by better packaging structure designs proposed in this study. Based on the above findings, this novel structure pressure sensor shows a high potential for membrane type micro-sensor application.

Highly Arsenic Doped CdTe Layers for the Back Contacts of CdTe Solar Cells

2007 ◽  
Vol 1012 ◽  
Author(s):  
Vincent Barrioz ◽  
Yuri Y. Proskuryakov ◽  
Eurig W. Jones ◽  
Jon D. Major ◽  
Stuart J.C. Irvine ◽  
...  
Keyword(s):  
Solar Cells ◽  
Series Resistance ◽  
Chemical Vapour ◽  
Cdte Layer ◽  
Open Circuit ◽  
Organic Chemical ◽  
Back Contact ◽  
Cdte Solar Cells ◽  
Current Voltage ◽  
Metal Organic

AbstractIn an effort to overcome the lack of a suitable metal as an ohmic back contact for CdTe solar cells, a study was carried out on the potential for using a highly arsenic (As) doped CdTe layer with metallization. The deposition of full CdTe/CdS devices, including the highly doped CdTe:As and the CdCl2 treatment, were carried out by metal organic chemical vapour deposition (MOCVD), in an all-in-one process with no etching being necessary. They were characterized and compared to control devices prepared using conventional bromine-methanol back contact etching. SIMS and C-V profiling results indicated that arsenic concentrations of up to 1.5 × 1019 at·cm-3 were incorporated in the CdTe. Current-voltage (J-V) characteristics showed strong improvements, particularly in the open-circuit voltage (Voc) and series resistance (Rs): With a 250 nm thick doped layer, the series resistance was reduced from 9.8 Ω·cm2 to 1.6 Ω·cm2 for a contact area of 0.25 cm2; the J-V curves displayed no rollover, while the Voc increased by up to 70 mV (~ 12 % rise). Preliminary XRD data show that there may be an As2Te3 layer at the CdTe surface which could be contributing to the low barrier height of this contact.

scholarly journals Scientific Investigations of a 16th Century Stall Belonging to the Evangelic Church in Bistriţa, Bistriţa-Năsăud County, Romania

2013 ◽  
Vol 2013 ◽  
pp. 1-5 ◽  
Author(s):  
C. Marutoiu ◽  
S. P. Grapini ◽  
A. Baciu ◽  
M. Miclaus ◽  
V. C. Marutoiu ◽  
...  
Keyword(s):  
Back Side ◽  
Front Side ◽  
X Ray Diffraction ◽  
Scanning Calorimetry ◽  
X Ray ◽  
Scientific Investigations ◽  
The Status ◽  
Dsc Analyses ◽  
The Church ◽  
Painting Layer

The Evangelic Church in Bistriţa city is one of the important gothic monuments in Romania. Inside the church there have been preserved a series of furniture pieces from different centuries, and the stall that has been analysed in this study is one of them. The study presents the investigations that were made on the occasion of restoring the stall. The nature and the status of the wooden supports and also the composition of the painting layer which covers the front side of the stall were investigated by several methods: Fourier transform infrared (FTIR) spectroscopy, X-ray diffraction (XRD), and differential scanning calorimetry (DSC) analyses. The back side of the stall was made of spruce fir wood and its status was also investigated. The nature of the component elements and the heritage value of the ensemble were also established.

Back Side Die Preparation for Check of Backend Related Problems

2006 ◽  
Author(s):  
Michael Huettinger ◽  
Uwe Papenberg ◽  
Jerome Touzel ◽  
Abel Janeiro ◽  
Ricardo Guedes ◽  
...  
Keyword(s):  
Preparation Method ◽  
Metal Layer ◽  
Back Side ◽  
Front Side ◽  
Top Down ◽  
Bottom Up ◽  
Root Cause

Abstract Damage on the top metal layer caused by backend packaging processes often results in unlocalizable electrical failures like column select fails in DRAM products. Consequently, crosssections through an exact address are unhelpful. Decapping from the front side of the die by removing the package (Top- Down preparation), only uncovers the damaged die area. The root cause is removed with the package. A preparation method that preserves the package at the failure (Bottom-Up preparation) is necessary. This paper presents a preparation method for investigations and assessment of backend related problems by removal of the Si-die from the back side, leaving the package and connections layers free for a quick and reliable review. Typical applications described here are the localization of imprint-originated fails or monitoring of the bonding processes.

FIB Micro-Surgery on Flip-Chips from the Backside

1998 ◽  
Author(s):  
Raymond Lee ◽  
Nicholas Antoniou
Keyword(s):  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Back Side ◽  
Bulk Silicon ◽  
Front Side ◽  
Large Hole ◽  
Area Of Interest ◽  
Flip Chip Packaging ◽  
Micro Surgery

Abstract The increasing use of flip-chip packaging is challenging the ability of conventional Focused Ion Beam (FIB) systems to perform even the most basic device modification and debug work. The inability to access the front side of the circuit has severely reduced the usefulness of tradhional micro-surgery. Advancements in FIB technology and its application now allow access to the circuitry from the backside through the bulk silicon. In order to overcome the problem of imaging through thick silicon, a microscope with Infra Red (IR) capability has been integrated into the FIB system. Navigation can now be achieved using the IR microscope in conjunction with CAD. The integration of a laser interferometer stage enables blind navigation and milling with sub-micron accuracy. To optimize the process, some sample preparation is recommended. Thinning the sample to a thickness of about 100 µm to 200 µm is ideal. Once the sample is thinned, it is then dated in the FIB and the area of interest is identified using the IR microscope. A large hole is milled using the FIB to remove most of the silicon covering the area of interest. At this point the application is very similar to more traditional FIB usage since there is a small amount of silicon to be removed in order to expose a node, cut it or reconnect it. The main differences from front-side applications are that the material being milled is conductive silicon (instead of dielectric) and its feature-less and therefore invisible to a scanned ion beam. In this paper we discuss in detail the method of back-side micro-surgery and its eflkcton device performance. Failure Analysis (FA) is another area that has been severely limited by flip-chip packaging. Localized thinning of the bulk silicon using FIB technology oflkrs access to diagnosing fdures in flip-chip assembled parts.

Development of a stress compensation layer for thin pixel modules 3D assembly

2014 ◽  
Vol 2014 (1) ◽  
pp. 000787-000793 ◽  
Author(s):  
G. Pares ◽  
T. McMullen ◽  
S. Tomé ◽  
L. Vignoud ◽  
R. Bates ◽  
...  
Keyword(s):  
Room Temperature ◽  
Flip Chip ◽  
Building Blocks ◽  
Back Side ◽  
Pixel Detector ◽  
Front Side ◽  
Radiation Length ◽  
Reflow Temperature ◽  
Solder Reflow ◽  
Deposition Conditions

The pixel modules are the fundamental building blocks of the ATLAS pixel detector system used in CERN LHC facility. They consist in their basic form of a silicon sensor that is flip-chipped bonded to a CMOS read-out integrated chip (ROIC). One of the main objectives for the ATLAS experiment is to develop an approach towards low mass modules and thus reducing radiation length. From the module perspective this can be achieved by using advanced 3D technology processes that includes the formation of copper and solder micro-bumps on top of the ROIC front-side, the thinning of both the sensor and the CMOS ROIC and finally the flip chip assembly of the 2 chips. The thinning of the silicon chips leads to low bump yield at the solder reflow stage due to bad co-planarity of the two chips creating dead zones within the pixel array. In the case of the ROIC, which is thinned to 100um, the chip bow varies from − 100 μm at room temperature to + 175 μm at reflow temperature resulting of CTE mismatch between materials in the CMOS stack and the silicon substrate. Our objective is to compensate dynamically the stress of the front side stack by adding a compensating layer to the back-side of the wafer. Utilising our material thermo-mechanical database coupled with a proprietary analytical simulator and measuring the bow of the ROIC at die level we are able to reduce the bow magnitude by approximately a factor of 3 by the introduction of the compensating layer. We show that it is possible to change the sign of the bow at room temperature after deposition of a SiN/Al:Si stack. This amplitude of the correction can be manipulated by the deposition conditions of the SiN/Al:Si stack. Further development of the backside deposition conditions are on-going where the target is to control the room temperature bow close to zero and reducing the bow magnitude throughout the full solder reflow temperature range hence conserving bump yield. In keeping with a 3D process the materials used are compatible with Through Silicon Via (TSV) technology with a TSV last approach in mind should we integrate this technology in the future.

Development of a Stress Compensation Layer for 3-D Assembly of Thin Pixel Modules

2015 ◽  
Vol 12 (1) ◽  
pp. 29-36
Author(s):  
G. Pares ◽  
T. McMullen ◽  
S. Tomé ◽  
L. Vignoud ◽  
R. Bates ◽  
...  
Keyword(s):  
Room Temperature ◽  
Flip Chip ◽  
Building Blocks ◽  
Back Side ◽  
Pixel Detector ◽  
Front Side ◽  
Radiation Length ◽  
Reflow Temperature ◽  
Solder Reflow ◽  
Deposition Conditions

Pixel modules are the fundamental building blocks of the ATLAS pixel detector system used in the CERN LHC facility. In their basic form, they consist of a silicon sensor that is flip-chip bonded to a CMOS read-out integrated chip (ROIC). One of the main objectives for the ATLAS experiment is to develop an approach toward low-mass modules, thus reducing radiation length. From the module perspective, this can be achieved by using advanced 3-D technology processes that include the formation of copper and solder microbumps on top of the ROIC front side, the thinning of both the sensor and the CMOS ROIC, and, finally, the flip-chip assembly of the two chips. The thinning of the silicon chips leads to low bump yield at the solder reflow stage, due to bad coplanarity of the two chips creating dead zones within the pixel array. In the case of the ROIC, which is thinned to 100 μm, the chip bow varies from −100 μm at room temperature to +175 μm at reflow temperature, resulting in CTE mismatch between materials in the CMOS stack and the silicon substrate. Our objective was to compensate dynamically for the stress of the front-side stack by adding a compensating layer to the back side of the wafer. Using our material thermomechanical database coupled with a proprietary analytical simulator, and measuring the bow of the ROIC at die level, we were able to reduce the bow magnitude by approximately a factor of 3 by introducing the compensating layer. We show that it is possible to change the sign of the bow at room temperature after deposition of a SiN/Al:Si stack. The amplitude of the correction can be manipulated by the deposition conditions of the SiN/Al:Si stack. Further development of the back-side deposition conditions are ongoing, where the target is to control the room temperature bow close to zero and reduce the bow magnitude throughout the full solder reflow temperature range, hence conserving bump yield. In keeping with a 3-D process, the materials used are compatible with through-silicon via (TSV) technology with a TSV-last approach in mind, should we integrate this technology in the future.

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