FIB Micro-Surgery on Flip-Chips from the Backside

1998 ◽  
Author(s):  
Raymond Lee ◽  
Nicholas Antoniou
Keyword(s):  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Back Side ◽  
Bulk Silicon ◽  
Front Side ◽  
Large Hole ◽  
Area Of Interest ◽  
Flip Chip Packaging ◽  
Micro Surgery

Abstract The increasing use of flip-chip packaging is challenging the ability of conventional Focused Ion Beam (FIB) systems to perform even the most basic device modification and debug work. The inability to access the front side of the circuit has severely reduced the usefulness of tradhional micro-surgery. Advancements in FIB technology and its application now allow access to the circuitry from the backside through the bulk silicon. In order to overcome the problem of imaging through thick silicon, a microscope with Infra Red (IR) capability has been integrated into the FIB system. Navigation can now be achieved using the IR microscope in conjunction with CAD. The integration of a laser interferometer stage enables blind navigation and milling with sub-micron accuracy. To optimize the process, some sample preparation is recommended. Thinning the sample to a thickness of about 100 µm to 200 µm is ideal. Once the sample is thinned, it is then dated in the FIB and the area of interest is identified using the IR microscope. A large hole is milled using the FIB to remove most of the silicon covering the area of interest. At this point the application is very similar to more traditional FIB usage since there is a small amount of silicon to be removed in order to expose a node, cut it or reconnect it. The main differences from front-side applications are that the material being milled is conductive silicon (instead of dielectric) and its feature-less and therefore invisible to a scanned ion beam. In this paper we discuss in detail the method of back-side micro-surgery and its eflkcton device performance. Failure Analysis (FA) is another area that has been severely limited by flip-chip packaging. Localized thinning of the bulk silicon using FIB technology oflkrs access to diagnosing fdures in flip-chip assembled parts.

Localizing IC Defect Using Nanoprobing: A 3D Approach

2019 ◽  
Author(s):  
Jane Y. Li ◽  
Chuan Zhang ◽  
John Aguada ◽  
Christopher Nemirow ◽  
Howard Marks
Keyword(s):  
Electron Beam ◽  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Multiple Perspectives ◽  
Site Specific ◽  
Root Cause ◽  
Area Of Interest ◽  
Defect Localization ◽  
Cmos Ic

Abstract This paper demonstrates a methodology for chip level defect localization that allows complex logic nets to be approached from multiple perspectives during failure analysis of modern flip-chip CMOS IC devices. By combining chip backside deprocessing with site-specific plasma Focused Ion Beam (pFIB) low angle milling, the area of interest in a failure IC device is made accessible from any direction for nanoprobing and Electron Beam Absorbed Current (EBAC) analysis. This methodology allows subtle defects to be more accurately localized and analyzed for thorough root-cause understanding.

Pulse Laser Ablation Techniques for IC Package Substrate Modifications and Validation

2016 ◽  
Author(s):  
Matthew M. Mulholland ◽  
Ahmed A. Helmy ◽  
Anthony V. Dao
Keyword(s):  
Integrated Circuits ◽  
Failure Analysis ◽  
Pulse Laser ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Back Side ◽  
Front Side ◽  
Local Approach ◽  
Ic Package ◽  
Level Analysis

Abstract Post silicon validation techniques specifically Focused Ion Beam (FIB) circuit editing and Failure Analysis (FA) require sample preparation on Integrated Circuits (IC). Although these preparation techniques are typically done globally across the encapsulated and silicon packaging materials, in some scenarios with tight mechanical or thermal boundary conditions, only a local approach can be attempted for the analysis. This local approach to access the underlying features, such as circuits, solder bumps, and electrical traces can be divided into two modification approaches. The back side approach is typically done for die level analysis by de-processing through encapsulated mold compound and silicon gaining access to the silicon transistor level. On the other hand, the front side approach is typically used for package level analysis by de-processing the ball grid array (BGA) and package substrate layers. Both of these local de-processing approaches can be done by using the conventional Laser Chemical Etching (LCE) platforms. The focus of this paper will be to investigate a front side modification approach to provide substrate material removal solutions. Process details and techniques will be discussed to gain access to metal signals for further failure analysis and debug. A pulse laser will be used at various processing stages to de-process IC package substrate materials.

Modeling and Optimizing XeF2-enhanced FIB Milling of Silicon

1999 ◽  
Author(s):  
Neil J. Bassom ◽  
Tung Mai
Keyword(s):  
Enhancement Factor ◽  
Material Removal ◽  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Beam Current ◽  
Back Side ◽  
Dose Enhancement ◽  
Average Current Density ◽  
Milling Parameters

Abstract Wide variations in the dose enhancement factor observed when milling silicon using Focused Ion Beam (FIB) XeF2 Gas Assisted Etching (GAE) prompted the development of a simple model of the GAE process. The model accounts for three material removal mechanisms: regular sputtering; gas-assisted sputtering; and spontaneous chemical reactions. An expression linking the dose enhancement factor, εd, to the gas and milling parameters has been derived. Experiments show that εd behaves as predicted; good quantitative agreement is achieved over wide ranges of milling parameters for εd values between 20X and 2500X. Conditions required to minimize variations in d and maximize material removal rates, M, are derived. It is shown that if the dose per unit area per raster is below a threshold value then εd and M depend only on the average current density J (the area of the box divided by the beam current). A consideration of the J regimes used for front-side and back-side FIB work shows why changes in εd have not previously been a problem but are inevitable when milling the large trenches characteristics of Flip Chip circuit modification work. While εd changes dramatically there is a region of J values for which M is approximately constant.

Focused Ion Beam Circuit Edit on Copper Redistribution Layer

2012 ◽  
Author(s):  
Lorenzo Motta ◽  
Paolo Veneto ◽  
Mark Antolik ◽  
Donato Di Donato
Keyword(s):  
Focused Ion Beam ◽  
Ion Beam ◽  
Fault Isolation ◽  
Three Dimensions ◽  
Back Side ◽  
Success Rates ◽  
Front Side ◽  
Continuous Development ◽  
Cu Metallization ◽  
Reduced Time

Abstract Focused ion beam (FIB) circuit edit (CE) is an integral part of IC debug, fault-isolation, and low yield analysis. Regarding FIB microsurgery, complexity is growing with the shrinking of dimensions of lower level metallization while the redistribution layer (RDL) structures can increase in all three dimensions. This requires continuous development of CE processes to address these opposite dimension trends and material variations. There are two venues to address CE, accessing from the front side (FS) or from the back side (BS) of an IC. This paper describes the FS techniques and methodologies developed to edit the RDL technology. The goal of this work is to demonstrate on a Cu GND/power plane the performance of the halogen-based contamination process. Results shows that the benefit of reduced time to remove thick Cu metallization is surely advantageous for CE throughput as well as for improving edit success rates.

Automatic Determination of Optimal FIB Operations for Improved Circuit Probing and Fast Reconfiguration

2000 ◽  
Author(s):  
Romain Desplats ◽  
Timothee Dargnies ◽  
Jean-Christophe Courrege ◽  
Philippe Perdu ◽  
Jean-Louis Noullet
Keyword(s):  
Integrated Circuit ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Semiconductor Devices ◽  
Front Side ◽  
Automatic Determination ◽  
Metal Line ◽  
New Approach ◽  
Metal Layers

Abstract Focused Ion Beam (FIB) tools are widely used for Integrated Circuit (IC) debug and repair. With the increasing density of recent semiconductor devices, FIB operations are increasingly challenged, requiring access through 4 or more metal layers to reach a metal line of interest. In some cases, accessibility from the front side, through these metal layers, is so limited that backside FIB operations appear to be the most appropriate approach. The questions to be resolved before starting frontside or backside FIB operations on a device are: 1. Is it do-able, are the metal lines accessible? 2. What is the optimal positioning (e.g. accessing a metal 2 line is much faster and easier than digging down to a metal 6 line)? (for the backside) 3. What risk, time and cost are involved in FIB operations? In this paper, we will present a new approach, which allows the FIB user or designer to calculate the optimal FIB operation for debug and IC repair. It automatically selects the fastest and easiest milling and deposition FIB operations.

Localization Techniques on a 0.15um CMOS Device: Charge Pump Failure Analysis

2002 ◽  
Author(s):  
Hui Pan ◽  
Thomas Gibson
Keyword(s):  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Charge Pump ◽  
Front Side ◽  
Pump Failure ◽  
Electrical Failure ◽  
Optical Proximity Correction ◽  
A Charge

Abstract In recent years, there have been many advances in the equipment and techniques used to isolate faults. There are many options available to the failure analyst. The available techniques fall into the categories of electrical, photonic, thermal and electron/ion beam [1]. Each technique has its advantages and its limitations. In this paper, we introduce a case of successful failure analysis using a combination of several fault localization techniques on a 0.15um CMOS device with seven layers of metal. It includes electrical failure mode characterization, front side photoemission, backside photoemission, Focused Ion Beam (FIB), Scanning Electron Microscope (SEM) and liquid crystal. Electrical characterization along with backside photoemission proved most useful in this case as a poly short problem was found to be causing a charge pump failure. A specific type of layout, often referred to as a hammerhead layout, and the use of Optical Proximity Correction (OPC) contributed to the poly level shorts.

Manufacturing In-Line Whole Wafer Focused Ion Beam (FIB) Memory Address Descramble Verification

2008 ◽  
Author(s):  
Steven B. Herschbein ◽  
Hyoung H. Kang ◽  
Scott L. Jansen ◽  
Andrew S. Dalton
Keyword(s):  
Flip Chip ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Random Access ◽  
Cell Counting ◽  
Test Results ◽  
Laboratory Procedure ◽  
Memory Array ◽  
Dual Beam ◽  
Process Level

Abstract Test engineers and failure analyst familiar with random access memory arrays have probably encountered the frustration of dealing with address descrambling. The resulting nonsequential internal bit cell counting scheme often means that the location of the failing cell under investigation is nowhere near where it is expected to be. A logical to physical algorithm for decoding the standard library block might have been provided with the design, but is it still correct now that the array has been halved and inverted to fit the available space in a new processor chip? Off-line labs have traditionally been tasked with array layout verification. In the past, hard and soft failures could be induced on the frontside of finished product, then bitmapped to see if the sites were in agreement. As density tightened, flip-chip FIB techniques to induce a pattern of hard fails on packaged devices came into practice. While the backside FIB edit method is effective, it is complex and expensive. The installation of an in-line Dual Beam FIB created new opportunities to move FA tasks out of the lab and into the FAB. Using a new edit procedure, selected wafers have an extensive pattern of defects 'written' directly into the memory array at an early process level. Bitmapping of the RAM blocks upon wafer completion is then used to verify correlation between the physical damaged cells and the logical sites called out in the test results. This early feedback in-line methodology has worked so well that it has almost entirely displaced the complex laboratory procedure of backside FIB memory array descramble verification.

An Infrared Microscope for Use on a Focused Ion Beam for Circuit Edit and Backside Edit Applications

2015 ◽  
Author(s):  
Alexander Richards ◽  
Matthew Weschler ◽  
Michael Durller
Keyword(s):  
Focused Ion Beam ◽  
Near Infrared ◽  
Ion Beam ◽  
Visible Spectrum ◽  
Camera System ◽  
Buried Structures ◽  
Ir Camera ◽  
Area Of Interest ◽  
Near Ultraviolet ◽  
Infrared Microscope

Abstract To help solve the navigational problem, i.e., being able to successfully locate a circuit for probing or editing without destroying chip functionality, a near-infrared (NIR), near-ultraviolet (NUV), and visible spectrum camera system was developed that attaches to most focused ion beam (FIB) or scanning electron microscope vacuum chambers. This paper reviews the details of the design and implementation of the NIR/NUV camera system, as instantiated upon the FEI FIB 200, with a particular focus on its use for the visualization of buried structures, and also for non-destructive real time area of interest location and end point detection. It specifically considers the use of the micro-optical camera system for its benefit in assisting with frontside and backside circuit edit, as well as other typical FIB milling activities. The quality of the image obtained by the IR camera rivals or exceeds traditional optical based imaging microscopy techniques.

A Novel Deprocessing Technique for Revealing Transistor-Level Damage on 7nm FinFET Devices

2020 ◽  
Author(s):  
Fei Long Xu ◽  
Phoumra Tan ◽  
Dan Nuez
Keyword(s):  
High Resolution ◽  
Flip Chip ◽  
Fault Localization ◽  
Wet Etching ◽  
Efficient Technique ◽  
Solid Immersion Lens ◽  
Front Side ◽  
Flip Chip Packaging ◽  
Metal Layers

Abstract Physical FA innovations in advanced flip-chip devices are essential, especially for die-level defects. Given the increasing number of metal layers, traditional front-side deprocessing requires a lot of work on parallel lapping and wet etching before reaching the transistor level. Therefore, backside deprocessing is often preferred for checking transistor-level defects, such as subtle ESD damage. This paper presents an efficient technique that involves precise, automated die thinning (from 760µm to 5µm), high-resolution fault localization using a solid immersion lens, and rigorous KOH etch. Using this technique, transistor-level damage was revealed on advanced 7nm FinFET devices with flip-chip packaging.

EBIC and XTEM Analysis of High Voltage SMOS Reliability Failures

2002 ◽  
Vol 716 ◽  
Author(s):  
Larry Rice
Keyword(s):  
High Voltage ◽  
Focused Ion Beam ◽  
Semiconductor Device ◽  
Ion Beam ◽  
Electrical Characterization ◽  
Operating Conditions ◽  
Oxide Semiconductor ◽  
Power Transistors ◽  
Area Of Interest ◽  
Transmission Electron

AbstractMicroscopists are faced with many challenges in locating and examining failure sites in the ever-shrinking semiconductor device. The site must be located using electrical characterization techniques like electron beam induced current (EBIC), photo emission microscopy (PEM) or liquid crystal (LC) and then cross-sectioned with a focused ion beam (FIB). Both PEM and LC require the semiconductor circuit to be running near operating conditions which has been observed to locally melt the area of interest, frequently destroying evidence of the failure mechanism. In contrast, EBIC typically can be accomplished at low or no applied voltage eliminating further damage to the circuit. EBIC has been applied to locate leakage sites in high voltage metal oxide semiconductor (MOS) electro static discharge (ESD) reliability failures. In addition to a brief revisit of the basic principles of EBIC and describing a technique to successfully cross section ‘hot spots’ for transmission electron microscopy (TEM) observation, focus will be placed on a case study of the reliability testing failure analysis of ESD power transistors using EBIC, SEM, focused ion beam (FIB), and XTEM.

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