Modeling and Fabrication of Cladded Ge Quantum Dot Gate Silicon MOSFETs Exhibiting 3-State Behavior

2008 ◽  
Vol 1108 ◽  
Author(s):  
Faquir C. Jain ◽  
Mukesh Gogna ◽  
Fuad Alamoody ◽  
Supriya Karmakar ◽  
Ernesto Suarez ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Threshold Voltage ◽  
Intermediate State ◽  
Gate Voltage ◽  
Inversion Layer ◽  
Similar Increase ◽  
State Behavior ◽  
Charge Neutralization ◽  
Ge Quantum Dot ◽  
State Device

AbstractThis paper presents electrical transfer (Id-Vg) and output (Id-Vds) characteristics of a GeOx-cladded-Ge quantum dot (QD) gate Si MOSFET devices. In QD gate FETs, the manifestation of an intermediate state ‘i” makes it a 3-state device. The intermediate state originates due to compensation of increment in the gate voltage by a similar increase in the threshold voltage, which occurs via charge neutralization in the QD gate due to transfer of charge from the inversion layer to either first or second of the two QD layers.

Modeling of Quantum Dot Channel (QDC) Si FETs at Sub-Kelvin for Multi-State Logic

2020 ◽  
Vol 29 (01n04) ◽  
pp. 2040017
Author(s):  
F. Jain ◽  
R. H. Gudlavalleti ◽  
R. Mays ◽  
B. Saman ◽  
J. Chandy ◽  
...  
Keyword(s):  
Quantum Dots ◽  
Quantum Dot ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Inversion Layer ◽  
Consistent Solution ◽  
Oxide Barrier ◽  
Ge Quantum Dot ◽  
And Inversion

Multi-state room temperature operation of SiOx-cladded Si quantum dots (QD) and GeOx-cladded Ge quantum dot channel (QDC) field-effect transistors (FETs) and spatial wavefunction switched (SWS)-FETs have been experimentally demonstrated. This paper presents simulation of cladded Si and Ge quantum dot channel (QDC) field-effect transistors at 4.2°K and milli-Kelvin temperatures. An array of thin oxide barrier/cladding (∼1nm) on quantum dots forms a quantum dot superlattice (QDSL). A gradual channel approximation model using potential and inversion layer charge density nQM, obtained by the self-consistent solution of the Schrodinger and Poisson’s equations, is shown to predict I-V characteristics up to milli-Kelvin temperatures. Physics-based equivalent circuit models do not work below 53°K. However, they may be improved by adapting parameters derived from quantum simulations. Low-temperature operation improves noise margins in QDC- and SWS-FET based multi-bit logic, which dissipates lower power and comprise of fewer device count. In addition, the role of self-assembled cladded QDs with transfer gate provides a novel pathway to implement qubit processing.

scholarly journals Quantum Dot Gate FET Based Multi-Value Logic Sequential Circuits

2019 ◽  
Vol 8 (2S3) ◽  
pp. 1368-1372
Keyword(s):  
Quantum Dot ◽  
Threshold Voltage ◽  
Intermediate State ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Sequential Circuits ◽  
Circuit Parameter ◽  
Stable States ◽  
Effect Transistor ◽  
Circuit Elements

The design of multi value logic sequential circuits based on QG-FET (Quantum dot Gate Field Effect Transistor) is discussed here. The QG-FET produces an intermediate state in between the two stable states(i.e.) ON & OFF, this is happening due to change in the threshold voltage over this range. The design of various sequential circuits using QDGFET which includes ternary D-flipflop and ternary right shift register is discussed. The proposed design of sequential circuits using QDGFET results an improved circuit parameter and less circuit elements in the implantation. The three state QG-FET will increase the bit handling capability of the device due to increase in number of states. So that, with less circuit elements at a time we can handle more number of bits.

Modeling of Multi-State Si and Ge Cladded Quantum Dot Gate FETs Using Verilog and ABM Simulations

2019 ◽  
Vol 28 (03n04) ◽  
pp. 1940026
Author(s):  
R. H. Gudlavalleti ◽  
B. Saman ◽  
R. Mays ◽  
M. Lingalugari ◽  
E. Heller ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Field Effect Transistors ◽  
Simulation Models ◽  
Logic Gates ◽  
State Behavior ◽  
Analog To Digital ◽  
Si Quantum Dot ◽  
Ge Quantum Dot ◽  
Gate Region ◽  
Analog Behavior

Quantum dot gate (QDG) field-effect transistors (FETs) fabricated using Si and Ge quantum dot layers, self-assembled in the gate region over the tunnel oxide, have exhibited 3- and 4-state behavior applicable for ternary and quaternary logic, respectively. This paper presents simulation of QDG-FETs comprising mixed Ge and Si quantum dot layers over tunnel oxide using an analog behavior model (ABM) and Verilog model. The simulations reproduce the experimental I-V characteristics of a fabricated mixed dot QDG-FET. GeOx-cladded Ge quantum dot layer is in interface to the tunnel oxide and is deposited over with a SiOx-cladded Si quantum dot layer. The fabricated QDG-FET has one source and one gate. The ABM simulation models QDG-FET using conventional BSIM 3V3 FETs with capacitances and other device parameters. In addition, VERILOG model is presented. The agreement in circuit and quantum simulations and experimental data will further advance in the designing of QDG-FET-based analog-to-digital converters (ADCs), 2-bit logic gates and SRAM cells.

1200 V SiC IE-UMOSFET with Low On-Resistance and High Threshold Voltage

2017 ◽  
Vol 897 ◽  
pp. 497-500 ◽  
Author(s):  
Shinsuke Harada ◽  
Yusuke Kobayashi ◽  
A. Kinoshita ◽  
N. Ohse ◽  
Takahito Kojima ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Gate Voltage ◽  
Gate Oxide ◽  
Critical Issue ◽  
High Threshold ◽  
Trade Off ◽  
Negative Gate Voltage

A critical issue with the SiC UMOSFET is the need to develop a shielding structure for the gate oxide at the trench bottom without any increase in the JFET resistance. This study describes our new UMOSFET named IE-UMOSFET, which we developed to cope with this trade-off. A simulation showed that a low on-resistance is accompanied by an extremely low gate oxide field even with a negative gate voltage. The low RonA was sustained as Vth increases. The RonA values at VG=25 V (Eox=3.2 MV/cm) and VG=20V (Eox=2.5 MV/cm), respectively, for the 3mm x 3mm device were 2.4 and 2.8 mWcm2 with a lowest Vth of 2.4 V, and 3.1 and 4.4 mWcm2 with a high Vth of 5.9 V.

Nitride-stressor and quantum-size engineering in Ge quantum-dot photoluminescence wavelength and exciton lifetime

Nano Futures ◽  
2020 ◽  
Vol 4 (1) ◽  
pp. 015001
Author(s):  
Yu-Hong Kuo ◽  
Shih-Hsuan Chiu ◽  
Che-Wei Tien ◽  
Sheng-Di Lin ◽  
Wen-Hao Chang ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Quantum Size ◽  
Exciton Lifetime ◽  
Ge Quantum Dot

Optical Transitions in a Self-Assembled Ge Quantum Dot/Si Superlattice Measured by Photoreflectance Spectroscopy

2005 ◽  
Vol 44 (No. 33) ◽  
pp. L1045-L1047
Author(s):  
Chie-In Lee ◽  
Yan-Ten Lu ◽  
Yan-Kuin Su ◽  
Shoou-Jinn Chang ◽  
Jenn-Shyong Hwang ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Optical Transitions ◽  
Photoreflectance Spectroscopy ◽  
Self Assembled ◽  
Ge Quantum Dot

Study on Fabrication and Fast Switching of High Voltage SiC JFET

2013 ◽  
Vol 827 ◽  
pp. 282-286
Author(s):  
Gang Chen ◽  
Song Bai ◽  
Run Hua Huang ◽  
Yong Hong Tao ◽  
Ao Liu
Keyword(s):  
Gate Voltage ◽  
Room Temperature ◽  
Inversion Layer ◽  
Oxide Semiconductor ◽  
Low Loss ◽  
Semiconductor Interface ◽  
Fast Switching ◽  
High Temperature Operation ◽  
Off Time ◽  
Channel Region

SiC devices have excellent properties such as ultra low loss, high withstand voltage, large capacity, high frequency, and high temperature operation compared with Si devices. The SiC JFET is expected to be appropriate for the power device because a JFET has no oxide-semiconductor interface in the channel region and does not use the low mobility SiC MOSFET inversion layer as a channel. Forward I-V up to 4A for SiC VJFET, Gate voltage from 2V to 3.5V by step 0.5V. Reverse I-V characteristics up to 4500V (VG=-8V) for SiC VJFET, Gate voltage from-4V to-8V by step-2V. Turn-off characteristics are studied and fast turn-off time of 136ns at room temperature under DC voltage of 600V is successfully demonstrated.

Strain and Phonon Confinement in Self-Assembled Ge Quantum Dot Superlattices

2003 ◽  
Vol 20 (11) ◽  
pp. 2001-2003 ◽  
Author(s):  
Yang Zheng ◽  
Shi Yi ◽  
Liu Jian-Lin ◽  
Yan Bo ◽  
Huang Zhuang-Xiong ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Phonon Confinement ◽  
Self Assembled ◽  
Ge Quantum Dot
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