Study on Fabrication and Fast Switching of High Voltage SiC JFET

2013 ◽  
Vol 827 ◽  
pp. 282-286
Author(s):  
Gang Chen ◽  
Song Bai ◽  
Run Hua Huang ◽  
Yong Hong Tao ◽  
Ao Liu
Keyword(s):  
Gate Voltage ◽  
Room Temperature ◽  
Inversion Layer ◽  
Oxide Semiconductor ◽  
Low Loss ◽  
Semiconductor Interface ◽  
Fast Switching ◽  
High Temperature Operation ◽  
Off Time ◽  
Channel Region

SiC devices have excellent properties such as ultra low loss, high withstand voltage, large capacity, high frequency, and high temperature operation compared with Si devices. The SiC JFET is expected to be appropriate for the power device because a JFET has no oxide-semiconductor interface in the channel region and does not use the low mobility SiC MOSFET inversion layer as a channel. Forward I-V up to 4A for SiC VJFET, Gate voltage from 2V to 3.5V by step 0.5V. Reverse I-V characteristics up to 4500V (VG=-8V) for SiC VJFET, Gate voltage from-4V to-8V by step-2V. Turn-off characteristics are studied and fast turn-off time of 136ns at room temperature under DC voltage of 600V is successfully demonstrated.

scholarly journals An Empirical Modeling of Gate Voltage-Dependent Behaviors of Amorphous Oxide Semiconductor Thin-Film Transistors including Consideration of Contact Resistance and Disorder Effects at Room Temperature

Membranes ◽  
2021 ◽  
Vol 11 (12) ◽  
pp. 954
Author(s):  
Sungsik Lee
Keyword(s):  
Contact Resistance ◽  
Gate Voltage ◽  
Room Temperature ◽  
Empirical Modeling ◽  
Oxide Semiconductor ◽  
Gate Bias ◽  
Channel Conductance ◽  
Disorder Effects ◽  
Amorphous Oxide Semiconductor ◽  
Voltage Dependent

In this paper, we present an empirical modeling procedure to capture gate bias dependency of amorphous oxide semiconductor (AOS) thin-film transistors (TFTs) while considering contact resistance and disorder effects at room temperature. From the measured transfer characteristics of a pair of TFTs where the channel layer is an amorphous In-Ga-Zn-O (IGZO) AOS, the gate voltage-dependent contact resistance is retrieved with a respective expression derived from the current–voltage relation, which follows a power law as a function of a gate voltage. This additionally allows the accurate extraction of intrinsic channel conductance, in which a disorder effect in the IGZO channel layer is embedded. From the intrinsic channel conductance, the characteristic energy of the band tail states, which represents the degree of channel disorder, can be deduced using the proposed modeling. Finally, the obtained results are also useful for development of an accurate compact TFT model, for which a gate bias-dependent contact resistance and disorder effects are essential.

ANOMALOUS LENGTH DEPENDENCE OF THE CONDUCTANCE OF A 2D CHANNEL NEAR THE THRESHOLD

1994 ◽  
Vol 08 (07) ◽  
pp. 445-454
Author(s):  
M. E. RAIKH ◽  
F. G. PIKUS
Keyword(s):  
Metal Oxide ◽  
Gate Voltage ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Channel Length ◽  
Metal Oxide Semiconductor ◽  
Potential Profile ◽  
Oxide Semiconductor ◽  
Assisted Tunneling ◽  
Channel Region

The modification of the potential profile in the channel of metal oxide semiconductor field effect transistors, caused by electrons in n+ contacts attracted to the surface by the gate voltage, is considered. Effective narrowing of the channel region, in which the transport is due to the phonon-assisted tunneling, could be responsible for the dramatic increase of the conductance with channel length in the strongly localized regime, as observed by Popović, Fowler, and Washburn.1

Energy spectrum in the inversion layer of a disordered oxide-semiconductor interface

1987 ◽  
Vol 179 (3) ◽  
pp. A20
Author(s):  
C. Papatriantafillou ◽  
A. Papakitsos ◽  
C. Paraskevaidis
Keyword(s):  
Energy Spectrum ◽  
Inversion Layer ◽  
Oxide Semiconductor ◽  
Semiconductor Interface

Energy spectrum in the inversion layer of a disordered oxide-semiconductor interface

1987 ◽  
Vol 179 (2-3) ◽  
pp. 527-539
Author(s):  
C. Papatriantafillou ◽  
A. Papakitsos ◽  
C. Paraskevaidis
Keyword(s):  
Energy Spectrum ◽  
Inversion Layer ◽  
Oxide Semiconductor ◽  
Semiconductor Interface

Development of 8 mΩ-cm2, 1.8 kV 4H-SiC DMOSFETs

2006 ◽  
Vol 527-529 ◽  
pp. 1261-1264 ◽  
Author(s):  
Sei Hyung Ryu ◽  
Sumi Krishnaswami ◽  
Brett A. Hull ◽  
Bradley Heath ◽  
Mrinal K. Das ◽  
...  
Keyword(s):  
Threshold Voltage ◽  
Room Temperature ◽  
Elevated Temperatures ◽  
Gate Length ◽  
Gate Bias ◽  
Low Loss ◽  
Layer Resistance ◽  
Switching Characteristics ◽  
Mos Gate ◽  
Drift Layer

8 mΩ-cm2, 1.8 kV power DMOSFETs in 4H-SiC are presented in this paper. A 0.5 μm long MOS gate length was used to minimize the MOS channel resistance. The DMOSFETs were able to block 1.8 kV with the gate shorted to the source. At room temperature, a specific onresistance of 8 mΩ-cm2 was measured with a gate bias of 15 V. At 150 oC, the specific onresistance increased to 9.6 mΩ-cm2. The increase in drift layer resistance due to a decrease in bulk electron mobility was partly cancelled out by the negative shift in MOS threshold voltage at elevated temperatures. The device demonstrated extremely fast, low loss switching characteristics. A significant improvement in converter efficiency was observed when the 4H-SiC DMOSFET was used instead of an 800 V silicon superjunction MOSFET in a simple boost converter configuration.

Improving the accuracy of the charge-sheet model for the long-channel metal-oxide semiconductor field-effect transistor

1987 ◽  
Vol 65 (8) ◽  
pp. 995-998
Author(s):  
N. G. Tarr
Keyword(s):  
Metal Oxide ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Inversion Layer ◽  
Potential Drop ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Analytic Approximation ◽  
Effect Transistor ◽  
Long Channel

It is shown that the accuracy of the charge-sheet model for the long-channel metal-oxide-semiconductor field-effect transistor can be improved by allowing for the small potential drop across the inversion layer, and by using a more accurate analytic approximation for the charge stored in the depletion region.

Modeling and Fabrication of Cladded Ge Quantum Dot Gate Silicon MOSFETs Exhibiting 3-State Behavior

2008 ◽  
Vol 1108 ◽  
Author(s):  
Faquir C. Jain ◽  
Mukesh Gogna ◽  
Fuad Alamoody ◽  
Supriya Karmakar ◽  
Ernesto Suarez ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Threshold Voltage ◽  
Intermediate State ◽  
Gate Voltage ◽  
Inversion Layer ◽  
Similar Increase ◽  
State Behavior ◽  
Charge Neutralization ◽  
Ge Quantum Dot ◽  
State Device

AbstractThis paper presents electrical transfer (Id-Vg) and output (Id-Vds) characteristics of a GeOx-cladded-Ge quantum dot (QD) gate Si MOSFET devices. In QD gate FETs, the manifestation of an intermediate state ‘i” makes it a 3-state device. The intermediate state originates due to compensation of increment in the gate voltage by a similar increase in the threshold voltage, which occurs via charge neutralization in the QD gate due to transfer of charge from the inversion layer to either first or second of the two QD layers.

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