Near-interface Traps in n-type SiO2/SiC MOS Capacitors from Energy-resolved CCDLTS

2010 ◽  
Vol 1246 ◽  
Author(s):  
Alberto F Basile ◽  
Sarit Dhar ◽  
John Rozen ◽  
Xudong Chen ◽  
John Williams ◽  
...  
Keyword(s):  
Silicon Dioxide ◽  
Electron Emission ◽  
Deep Level Transient Spectroscopy ◽  
Deep Level ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Interface Traps ◽  
Emission Rates ◽  
Mos Capacitors ◽  
Transient Spectroscopy

AbstractSilicon Carbide (SiC) Metal-Oxide-Semiconductor (MOS) capacitors, having different nitridation times, were characterized by means of Constant Capacitance Deep Level Transient Spectroscopy (CCDLTS). Electron emission was investigated with respect to the temperature dependence of emission rates and the amplitude of the signal as a function of the filling voltage. The comparison between the emission activation energies of the dominant CCDLTS peaks and the filling voltages, led to the conclusion that the dominant trapping behavior originates in the Silicon-dioxide (SiO2) layer. Moreover, a model of electron capture via tunneling can explain the dependence of the CCDLTS signal on increasing filling voltage.

On Separating Oxide Charges and Interface Charges in 4H-SiC Metal-Oxide-Semiconductor Devices

2006 ◽  
Vol 527-529 ◽  
pp. 1007-1010 ◽  
Author(s):  
Daniel B. Habersat ◽  
Aivars J. Lelis ◽  
G. Lopez ◽  
J.M. McGarrity ◽  
F. Barry McLean
Keyword(s):  
Room Temperature ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Interface Traps ◽  
Mos Capacitors ◽  
Mos Devices ◽  
Interface Charges ◽  
Flatband Voltage ◽  
Oxide Traps ◽  
P Type

We have investigated the distribution of oxide traps and interface traps in 4H Silicon Carbide MOS devices. The density of interface traps, Dit, was characterized using standard C-V techniques on capacitors and charge pumping on MOSFETs. The number of oxide traps, NOT, was then calculated by measuring the flatband voltage VFB in p-type MOS capacitors. The amount that the measured flatband voltage shifts from ideal, minus the contributions due to the number of filled interface traps Nit, gives an estimate for the number of oxide charges present. We found Dit to be in the low 1011cm−2eV−1 range in midgap and approaching 1012 −1013cm−2eV−1 near the band edges. This corresponds to an Nit of roughly 2.5 ⋅1011cm−2 for a typical capacitor in flatband at room temperature. This data combined with measurements of VFB indicates the presence of roughly 1.3 ⋅1012cm−2 positive NOT charges in the oxide near the interface for our samples.

The Ion Implanted Arsenic Tail in Silicon

1989 ◽  
Vol 147 ◽  
Author(s):  
S. E. Beck ◽  
R. J. Jaccodine ◽  
C. Clark
Keyword(s):  
Silicon Dioxide ◽  
Thermal Annealing ◽  
Anodic Oxidation ◽  
Rapid Thermal Annealing ◽  
Deep Level Transient Spectroscopy ◽  
Deep Level ◽  
Electrical Activation ◽  
Spreading Resistance ◽  
Transient Spectroscopy ◽  
And Diffusion

AbstractRapid thermal annealed tail regions of shallow junction arsenic implants into silicon have been investigated. Tail profiles have been roduced by an anodic oxidation and stripping technique after implantation to fluences of 1014 to 1016 cm−2 and by implanting through a layer of silicon dioxide. Electrical activation and diffusion have been achieved by rapid thermal annealing in the temperature range of 800 to 1100 °C. Electrically active defects remain after annealing. Spreading resistance and deep level transient spectroscopy results are presented. The diffusion of the arsenic tail is discussed and compared with currently accepted models.

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