On Separating Oxide Charges and Interface Charges in 4H-SiC Metal-Oxide-Semiconductor Devices

2006 ◽  
Vol 527-529 ◽  
pp. 1007-1010 ◽  
Author(s):  
Daniel B. Habersat ◽  
Aivars J. Lelis ◽  
G. Lopez ◽  
J.M. McGarrity ◽  
F. Barry McLean
Keyword(s):  
Room Temperature ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Interface Traps ◽  
Mos Capacitors ◽  
Mos Devices ◽  
Interface Charges ◽  
Flatband Voltage ◽  
Oxide Traps ◽  
P Type

We have investigated the distribution of oxide traps and interface traps in 4H Silicon Carbide MOS devices. The density of interface traps, Dit, was characterized using standard C-V techniques on capacitors and charge pumping on MOSFETs. The number of oxide traps, NOT, was then calculated by measuring the flatband voltage VFB in p-type MOS capacitors. The amount that the measured flatband voltage shifts from ideal, minus the contributions due to the number of filled interface traps Nit, gives an estimate for the number of oxide charges present. We found Dit to be in the low 1011cm−2eV−1 range in midgap and approaching 1012 −1013cm−2eV−1 near the band edges. This corresponds to an Nit of roughly 2.5 ⋅1011cm−2 for a typical capacitor in flatband at room temperature. This data combined with measurements of VFB indicates the presence of roughly 1.3 ⋅1012cm−2 positive NOT charges in the oxide near the interface for our samples.

Investigation of Oxide Films Prepared by Direct Oxidation of C-Face 4H-SiC in Nitric Oxide

2010 ◽  
Vol 645-648 ◽  
pp. 515-518 ◽  
Author(s):  
Dai Okamoto ◽  
Hiroshi Yano ◽  
Yuki Oshiro ◽  
Tomoaki Hatayama ◽  
Yukiharu Uraoka ◽  
...  
Keyword(s):  
Field Effect ◽  
High Performance ◽  
Room Temperature ◽  
Field Effect Transistors ◽  
Gate Oxide ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Interface Traps ◽  
Direct Oxidation ◽  
Mos Capacitors

Characteristics of metal–oxide–semiconductor (MOS) capacitors and MOS field-effect transistors (MOSFETs) fabricated by direct oxidation of C-face 4H-SiC in NO were investigated. It was found that nitridation of the C-face 4H-SiC MOS interface generates near-interface traps (NITs) in the oxide. These traps capture channel mobile electrons and degrade the performance of MOSFETs. The NITs can be reduced by unloading the samples at room temperature after oxidation. It is important to reduce not only the interface states but also the NITs to fabricate high-performance C-face 4H-SiC MOSFETs with nitrided gate oxide.

Flatband Voltage Shift Depending on SiO2/SiC Interface Charges in 4H-SiC MOS Capacitors with AlON/SiO2 Stacked Gate Dielectrics

2016 ◽  
Vol 858 ◽  
pp. 681-684 ◽  
Author(s):  
Takuji Hosoi ◽  
Shuji Azumo ◽  
Kenji Yamamoto ◽  
Masatoshi Aketa ◽  
Yusaku Kashiwagi ◽  
...  
Keyword(s):  
Gate Dielectrics ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Aluminum Oxynitride ◽  
Equivalent Thickness ◽  
Mos Capacitors ◽  
Voltage Shift ◽  
Interface Charges ◽  
Linear Fit ◽  
Flatband Voltage

The mechanism of flatband voltage shift in SiC metal-oxide-semiconductor (MOS) capacitors with stacked gate dielectrics consisting of aluminum oxynitride (AlON) layers and SiO2 underlayers was investigated by varying the AlON and SiO2 thicknesses. The flatband voltages of the fabricated capacitors with fixed SiO2 underlayer thicknesses were almost independent of the AlON thickness, indicating the negligible charges in AlON layer. On the other hand, when varying SiO2 underlayer thickness, the flatband voltage decreased with an increase in capacitance equivalent thickness (CET), and the slope of their linear fit was comparable to that for SiC MOS capacitors without AlON layer. These observations can be well explained by assuming interface charges at AlON/SiO2 interface with an amount comparable, but a polarity opposite to, those at SiO2/SiC interface.

Effects of oxide traps, interface traps, and ‘‘border traps’’ on metal‐oxide‐semiconductor devices

1993 ◽  
Vol 73 (10) ◽  
pp. 5058-5074 ◽  
Author(s):  
D. M. Fleetwood ◽  
P. S. Winokur ◽  
R. A. Reber ◽  
T. L. Meisenheimer ◽  
J. R. Schwank ◽  
...  
Keyword(s):  
Metal Oxide ◽  
Semiconductor Devices ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Interface Traps ◽  
Oxide Traps

Near-interface Traps in n-type SiO2/SiC MOS Capacitors from Energy-resolved CCDLTS

2010 ◽  
Vol 1246 ◽  
Author(s):  
Alberto F Basile ◽  
Sarit Dhar ◽  
John Rozen ◽  
Xudong Chen ◽  
John Williams ◽  
...  
Keyword(s):  
Silicon Dioxide ◽  
Electron Emission ◽  
Deep Level Transient Spectroscopy ◽  
Deep Level ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Interface Traps ◽  
Emission Rates ◽  
Mos Capacitors ◽  
Transient Spectroscopy

AbstractSilicon Carbide (SiC) Metal-Oxide-Semiconductor (MOS) capacitors, having different nitridation times, were characterized by means of Constant Capacitance Deep Level Transient Spectroscopy (CCDLTS). Electron emission was investigated with respect to the temperature dependence of emission rates and the amplitude of the signal as a function of the filling voltage. The comparison between the emission activation energies of the dominant CCDLTS peaks and the filling voltages, led to the conclusion that the dominant trapping behavior originates in the Silicon-dioxide (SiO2) layer. Moreover, a model of electron capture via tunneling can explain the dependence of the CCDLTS signal on increasing filling voltage.

Alternative method of interface traps passivation by introducing of thin silicon nitride layer at 4H-SiC/SiO2 interface

2014 ◽  
Vol 1693 ◽  
Author(s):  
Aleksey I. Mikhaylov ◽  
Alexey V. Afanasyev ◽  
Victor V. Luchinin ◽  
Sergey A. Reshanov ◽  
Adolf Schöner
Keyword(s):  
Silicon Nitride ◽  
Silicon Oxide ◽  
Field Effect Transistors ◽  
Electrical Characterization ◽  
Nitride Layer ◽  
Oxide Semiconductor ◽  
Interface Traps ◽  
Mos Devices ◽  
Inversion Channel ◽  
P Type

ABSTRACTAn alternative approach for reduction of interface traps density at 4H-SiC/SiO2 interface is proposed. Silicon nitride / silicon oxide stack was deposited on p-type 4H-SiC (0001) epilayers and subsequently over-oxidized. The electrical characterization of the interface was done by employing metal-oxide semiconductor (MOS) devices, inversion-channel MOS devices and lateral MOS field effect transistors (MOSFETs).

Effect of Phosphorus Implantation Prior to Oxidation on Electrical Properties of Thermally Grown SiO2/4H-SiC MOS Structures

2014 ◽  
Vol 806 ◽  
pp. 133-138 ◽  
Author(s):  
Aleksey Mikhaylov ◽  
Tomasz Sledziewski ◽  
Alexey Afanasyev ◽  
Victor Luchinin ◽  
Sergey A. Reshanov ◽  
...  
Keyword(s):  
Electrical Properties ◽  
Reference Sample ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Phosphorus Concentration ◽  
Interface Traps ◽  
Mos Capacitor ◽  
Mos Devices ◽  
Dry Oxidation ◽  
Mos Structures

The electrical properties of metal-oxide-semiconductor (MOS) devices fabricated using dry oxidation on phosphorus-implanted n-type 4H-SiC (0001) epilayers have been investigated. MOS structures were compared in terms of interface traps and reliability with reference sample which was produced by dry oxidation under the same conditions. The notably lower interface traps density measured in MOS capacitor with phosphorus concentration exceeding 1018 cm-3 at the SiO2/SiC interface was attributed to interface traps passivation by incorporated phosphorus ions.

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