Vertical, Dual Gate CMOS Structure in Two Laser-Recrystallized Silicon Layers over Oxidized Silicon Substrate

MRS Proceedings ◽

10.1557/proc-33-155 ◽

1984 ◽

Vol 33 ◽

Author(s):

P. Kenyon ◽

H. Dressel ◽

A. Negri

Keyword(s):

Silicon Substrate ◽

Cmos Process ◽

Dual Gate ◽

Implant Technique ◽

Integrated Structures

ABSTRACTA seven mask CMOS process that provides vertically integrated structures with joint gates is described. The structures have been characterized as individual NMOS and PMOS transistors. An implant technique will be described which may permit the fabrication of fully self-aligned CMOS structures.

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TCAD-Based Assessment of Dual-Gate MISHEMT with Sapphire, SiC, and Silicon Substrate

IETE Technical Review ◽

10.1080/02564602.2019.1699455 ◽

2019 ◽

pp. 1-9 ◽

Cited By ~ 1

Author(s):

Preeti Singh ◽

Vandana Kumari ◽

Manoj Saxena ◽

Mridula Gupta

Keyword(s):

Silicon Substrate ◽

Dual Gate

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An AMC Backed Folded Dipole Slot Antenna Based on CMOS Process

International Journal of Antennas and Propagation ◽

10.1155/2013/351956 ◽

2013 ◽

Vol 2013 ◽

pp. 1-4 ◽

Cited By ~ 1

Author(s):

Guo Qing Luo ◽

Lin Qi Wu ◽

Xiao Hong Zhang

Keyword(s):

Surface Wave ◽

Dielectric Permittivity ◽

Silicon Substrate ◽

Slot Antenna ◽

Cmos Process ◽

Magnetic Conductor ◽

High Dielectric Permittivity ◽

On Chip ◽

Folded Dipole ◽

High Dielectric

A fold dipole slot antenna backed by artificial magnetic conductor (AMC) structure based on a standard 0.18 um CMOS process on chip application is firstly proposed in this paper. Conventional silicon antenna on chip (AoC) suffers from low radiation performance because the most electromagnetic energy is restricted in silicon substrate as surface wave for its high dielectric permittivity. The energy is dissipated as thermal for low resistivity of silicon substrate. AMC constructed by a periodic 6*6 square patch array is adopted as background to improve radiation performance of the proposed folded dipole slot AoC. Gain of the proposed AMC backed AoC is improved about 3.5 dB compared with that of the same AoC without AMC background.

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A Novel Maskless Post-CMOS Bulk Micromachining Process

Microelectromechanical Systems ◽

10.1115/imece2003-41721 ◽

2003 ◽

Author(s):

Jing-Hung Chiou ◽

Ching-Liang Dai ◽

Jen-Yi Chen ◽

Michael S.-C. Lu

Keyword(s):

Metal Oxide ◽

Silicon Substrate ◽

Complementary Metal Oxide Semiconductor ◽

Metal Oxide Semiconductor ◽

Wet Etching ◽

Oxide Semiconductor ◽

Cmos Process ◽

Deep Cavity ◽

Deep Cavities ◽

Tmah Solution

This work describes a new post-CMOS (Complementary Metal Oxide Semiconductor) bulk micromachining process for fabrication of various microstructures. The important feature of the post-CMOS process is the use of wet etching without an addition mask, to form various microstructures and deep cavities in the silicon substrate. The post-CMOS process starts with wet etching to remove sacrificial layers, which are stacked layers of metals and vias, to expose the silicon substrate. Then, KOH or TMAH solution is employed to etch the silicon substrate to form various deep cavities and suspended structures. Many suspended structures, which include beams, bridges and plates, are fabricated using the standard 0.35-μm SPFM (Single Polysilicon Four Metal) CMOS process and the post-CMOS process. Experimental results reveals that a plate with an area of 200×200 μm2, a bridge with a length of 300μm, and various beams with lengths from 100-μm to 400-μm suspended on a deep cavity were fabricated successfully.

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The Integration of the Ferromagnetic Inductors into the Standard CMOS Chip

MRS Proceedings ◽

10.1557/opl.2012.1413 ◽

2012 ◽

Vol 1427 ◽

Cited By ~ 1

Author(s):

Oleg Nizhnik ◽

Olinver M. Vinluan ◽

Kohei Higuchi ◽

Koji Sonoda ◽

Masatoshi Ishii ◽

...

Keyword(s):

Quality Factor ◽

Silicon Substrate ◽

Amorphous Material ◽

Passivation Layer ◽

Cmos Process ◽

Ion Etching ◽

Deep Reactive Ion Etching ◽

Ferrite Material ◽

Ferromagnetic Layers ◽

Cmos Chip

ABSTRACTAn inductor in standard CMOS process having an inductance of 52 nH and a quality factor of 1.5 at frequency equal to 80 Mhz was fabricated. The polymer passivation layer of the standard CMOS inductor was etched out. The silicon substrate under the inductor, having a thickness of 280 μm was also etched out by deep reactive ion etching (DRIE). Ferrite material ZnFe2O4 and amorphous material Fe4.7Co70.3Si15B10 was then sputtered on top of the inductor sequentially. The same sputtering procedure was also performed into the bottom of the inductor. The result is an inductor that is sandwiched by multiple ferromagnetic layers. The inductance of the new ferromagnetic inductor has increased by 15% from 52 nH to 60 nH. The quality factor has also increased by 20% from 1.5 to 1.8.

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