Time-Dependent Dielectric Breakdown in Thin Intrinsic SiO2 Films

1995 ◽  
Vol 391 ◽  
Author(s):  
J. S. Suehle ◽  
P. Chaparala

AbstractTime-Dependent Dielectric Breakdown studies were performed on 6.5-, 9-, 15-, 20-, and 22.5-nm thick SiO2 films over a wide range of stress temperatures and electric fields. Very high temperatures (400 °C) were used to accelerate breakdown so that stress tests could be performed at low electric fields close to those used for device operating conditions. The results indicate that the dependence of TDDB on electric field and temperature is different from that reported in earlier studies. Specifically, the electric-field-acceleration parameter is independent of temperature and the thermal activation energy was determined to be between 0.7 and 0.9 eV for stress fields below 7.0 MV/cm.Failure distributions of high-quality current-generation oxide films are shown to be of single mode and have dispersions that are not sensitive to stress electric field or temperature, unlike distributions observed for oxides examined in earlier studies. These results have implications on the choice of the correct physical model to describe TDDB in thin films. The data also demonstrate for the first time the reliability of silicon dioxide films at very high temperatures.

1995 ◽  
Vol 386 ◽  
Author(s):  
J. S. Suehle ◽  
P. Chaparala

ABSTRACTTime-Dependent Dielectric Breakdown studies were performed on 6.5-, 9-, 15-, 20-, and 22.5- nm thick SiO2 films over a wide range of stress temperatures and electric fields. Very high temperatures (400 °C) were used to accelerate breakdown so that stress tests could be performed at low electric fields close to those used for device operating conditions. The results indicate that the dependence of TDDB on electric field and temperature is different from that reported in earlier studies. Specifically, the electric-field-acceleration parameter is independent of temperature and the thermal activation energy was determined to be between 0.7 and 0.9 eV for stress fields below 7.0 MV/cm.Failure distributions of high-quality current-generation oxide films are shown to be of single mode and have dispersions that are not sensitive to stress electric field or temperature, unlike distributions observed for oxides examined in earlier studies. These results have implications on the choice of the correct physical model to describe TDDB in thin films. The data also demonstrate for the first time the reliability of silicon dioxide films at very high temperatures.


2008 ◽  
Vol 600-603 ◽  
pp. 1131-1134 ◽  
Author(s):  
Kevin Matocha ◽  
Zachary Stum ◽  
Steve Arthur ◽  
Greg Dunne ◽  
Ljubisa Stevanovic

SiC vertical MOSFETs were fabricated and characterized to achieve a blocking voltage of 950 Volts and a specific on-resistance of 8.4 mW-cm2. Extrapolations of time-dependent dielectric breakdown measurements versus applied electric field indicate that the gate oxide mean-time to failure is approximately 105 hours at 250°C.


2001 ◽  
Vol 41 (1) ◽  
pp. 47-52 ◽  
Author(s):  
A Teramoto ◽  
H Umeda ◽  
K Azamawari ◽  
K Kobayashi ◽  
K Shiga ◽  
...  

2007 ◽  
Vol 556-557 ◽  
pp. 675-678 ◽  
Author(s):  
Kevin Matocha ◽  
Richard Beaupre

Thermal oxides on 4H-SiC are characterized using time-dependent dielectric breakdown techniques at electric fields between 6 and 10 MV/cm. At 250°C, oxides thermally-grown using N2O with NO annealing achieve a mean time to failure (MTTF) of 2300 hours at 6 MV/cm. Oxides grown in steam with NO annealing show approximately four times longer MTTF than N2O-grown oxides. At electric fields greater than 8 MV/cm, Fowler-Nordheim tunneling significantly reduces the expected failure times. For this reason, extrapolation of mean-time to failure at low fields must be performed by datapoints measured at lower electric fields.


2004 ◽  
Vol 812 ◽  
Author(s):  
M. Engelhardt ◽  
G. Schindler ◽  
W. Steinhögl ◽  
G. Steinlesberger ◽  
M. Traving

AbstractSub-lithographic copper damascene lines were fabricated to investigate already today the physical phenomena and scaling limits of metallic conductors in the metallization systems of chip generations which are believed to be in production 10 years from now and later. Using standard manufacturing processes and state-of-the-art process tools, including standard lithography tools, narrow copper lines were fabricated at the expense of a relaxed pitch by use of a removable spacer technique. These copper nano interconnects were passivated and subjected to electrical measurements. Our results show that continuous down scaling to increase device performance will result in an unfavorable increase of the electrical resistivity of copper in stateof-the-art metallization schemes. Electrical measurements over a wide range of temperatures down to cryogenic temperatures reveal the limited potential of cooling to reduce resistivity of conductors as lateral dimensions will be shrinked down to the sub-100nm regime. By down scaling of copper diffusion barriers in damascene trenches, barrier functionality was demonstrated after high temperature anneals and excessive bias-temperature stress tests for films meeting or even exceeding end-of-roadmap thickness requirements. An analysis of the temperature dependence of the leakage current measured at very high electric fields applied between neighboring damascene lines suggests the conduction mechanism in the SiO2 used as intermetal dielectric to be Frenkel-Poole type rather than Schottky emission. Electromigration life times of sub-100nm copper lines embedded in oxide were found to be comparable with those obtained for similar structures fabricated with today's feature sizes.


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