Electrical Characterization of Ultra-Shallow Junctions Formed by Diffusion From a CoSi2 Diffusion Source

1996 ◽  
Vol 427 ◽  
Author(s):  
F. La Via ◽  
E. Rimini
Keyword(s):  
Electrical Characterization ◽  
Junction Depth ◽  
Thermal Budget ◽  
Shallow Junctions ◽  
Different Temperatures ◽  
Diffusion Source ◽  
Ultra Shallow Junctions ◽  
20 Nm ◽  
Low Thermal Budget

AbstractUltra-Shallow p+/n and n+/p junctions were fabricated using a Silicide-As-Diffusion-Source (SADS) process and a low thermal budget (800÷900 °C). A thin layer (50 nm) of CoSi2 was implanted with As and BF2 and subsequently diffused at different temperatures and times to form two Ultra-Shallow junctions with a junction depth of 14 and 20 nm. These diodes were extensively investigated by I-V and C-V measurements in the range of temperature between 80 and 500 K. TEM delineation was used to controll the junction uniformity.

Electrical characterization of low thermal budget gate oxides on Si/Si0.8Ge0.2/Si substrates

2002 ◽  
Vol 46 (7) ◽  
pp. 991-995 ◽  
Author(s):  
Alok Sareen ◽  
Ann-Chatrin Lindgren ◽  
Per Lundgren ◽  
Stefan Bengtsson
Keyword(s):  
Electrical Characterization ◽  
Gate Oxides ◽  
Thermal Budget ◽  
Si Substrates ◽  
Low Thermal Budget

Solid Phase Epitaxy process integration on 50-nm PMOS devices: Effects of defects on chemical and electrical characteristics of ultra shallow junctions

2004 ◽  
Vol 810 ◽  
Author(s):  
R. El Farhane ◽  
C. Laviron ◽  
F. Cristiano ◽  
N. Cherkashin ◽  
P. Morin ◽  
...  
Keyword(s):  
Process Integration ◽  
Solid Phase ◽  
Cmos Process ◽  
Solid Phase Epitaxy ◽  
Electrical Characteristics ◽  
Use Of Self ◽  
Thermal Budget ◽  
Shallow Junctions ◽  
Ultra Shallow Junctions ◽  
Low Thermal Budget

ABSTRACTWe demonstrate in this paper the viability of an ultra-low thermal budget CMOS process enabling the formation of ultra shallow junctions with competitive transistor characteristics. In particular, we demonstrate in this work the influence of defects on chemical and electrical results. It is shown that the use of self-amorphizing implantation with BF2for Source/Drain, reduces the junction leakage by two decades.

Electrical characterization of InGaAs ultra-shallow junctions

2010 ◽  
Vol 28 (1) ◽  
pp. C1C41-C1C47 ◽  
Author(s):  
Dirch H. Petersen ◽  
Ole Hansen ◽  
Peter Bøggild ◽  
Rong Lin ◽  
Peter F. Nielsen ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Shallow Junctions ◽  
Ultra Shallow Junctions

Vacancy Engineering – An Ultra-Low Thermal Budget Method for High-Concentration 'Diffusionless' Implantation Doping

2008 ◽  
Vol 573-574 ◽  
pp. 295-304 ◽  
Author(s):  
Nicholas E.B. Cowern ◽  
Andrew J. Smith ◽  
Nicholas S. Bennett ◽  
Brian J. Sealy ◽  
Russell Gwilliam ◽  
...  
Keyword(s):  
Low Temperatures ◽  
High Performance ◽  
Silicon Films ◽  
Doping Profile ◽  
Junction Depth ◽  
High Concentration ◽  
Thermal Budget ◽  
Boron Implantation ◽  
Ultra Shallow Junctions ◽  
Low Thermal Budget

This paper reviews the physics and the potential application of ion-implanted vacancies for high-performance B-doped ultra-shallow junctions. By treatment of silicon films with vacancygenerating implants prior to boron implantation, electrically active boron concentrations approaching 1021 cm-3 can be achieved by Rapid Thermal Annealing at low temperatures, without the use of preamorphisation. Source/drain (S/D) junctions formed by advanced vacancy engineering implants (VEI) are activated far above solubility. Furthermore, in the case of appropriately engineered thin silicon films, this activation is stable with respect to deactivation and the doping profile is practically diffusionless. Sheet resistance Rs is predicted to stay almost constant with decreasing junction depth Xj, thus potentially outperforming other S/D engineering approaches at the ‘32 nm node’ and beyond.

Process and Simulation of TiSi2/n+/p Silicon Shallow Junctions

1991 ◽  
Vol 235 ◽  
Author(s):  
Ying Wu ◽  
W. Savin ◽  
T. Fink ◽  
N. M. Ravindra ◽  
R. T. Lareau ◽  
...  
Keyword(s):  
Electrical Characterization ◽  
Furnace Annealing ◽  
Si Substrates ◽  
Conventional Furnace ◽  
Mass Spec ◽  
Current Voltage ◽  
Shallow Junctions ◽  
Current Voltage Characteristics ◽  
Secondary Ion

ABSTRACTExperimental analysis and simulation of the formation and electrical characterization of TiSi2/+/p-Si shallow junctions are presented here. The formation of shallow n+-p junction, by ion implantation of As through Ti films evaporated on p-Si substrates followed by Rapid Thermal Annealing (RTA) and conventional furnace annealing has been performed in these experiments. Structural techniques such as Secondary Ion Mass Spec-troscopy (SIMS) and Rutherford Backscattering (RBS) experiments have been employed to characterize these devices. RUMP simulations were used to analyze and interpret the RBS data. Current-voltage characteristics have been simulated using PISCES simulator.

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