The Effect of Roughness Features on Mos Surface Electric Field and Fowler-Nordheim Tunneling Behavior

1997 ◽  
Vol 473 ◽  
Author(s):  
Heng-Chih Lin ◽  
Edwin C. Kan ◽  
Toshiaki Yamanaka ◽  
Simon J. Fang ◽  
Kwame N. Eason ◽  
...  
Keyword(s):  
Electric Field ◽  
Three Dimensional ◽  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Interface Roughness ◽  
Normal Electric Field ◽  
Surface Electric Field ◽  
Tunneling Behavior ◽  
Nordheim Tunneling

ABSTRACTFor future CMOS GSI technology, Si/SiO2 interface micro-roughness becomes a non-negligible problem. Interface roughness causes fluctuations of the surface normal electric field, which, in turn, change the gate oxide Fowler-Nordheim tunneling behavior. In this research, we used a simple two-spheres model and a three-dimensional Laplace solver to simulate the electric field and the tunneling current in the oxide region. Our results show that both quantities are strong functions of roughness spatial wavelength, associated amplitude, and oxide thickness. We found that RMS roughness itself cannot fully characterize surface roughness and that roughness has a larger effect for thicker oxide in terms of surface electric field and tunneling behavior.

Gate Tunneling Current Predicting Model for Scaled NMOSFET Devices

2013 ◽  
Vol 772 ◽  
pp. 422-426
Author(s):  
Zhi Chao Zhao ◽  
Tie Feng Wu ◽  
Hui Bin Ma ◽  
Quan Wang ◽  
Jing Li
Keyword(s):  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Integral Approach ◽  
Predicting Model ◽  
Mos Devices ◽  
Gate Oxide Thickness ◽  
Novel Theory ◽  
Gate Tunneling ◽  
Thin Gate Oxide

With the scaling of MOS devices, gate tunneling current increases significantly due to thinner gate oxides, and static characteristics of devices and circuit are severely affected by the presence of gate tunneling currents. In this paper, a novel theory gate tunneling current predicting model using integral approach is presented in ultra-thin gate oxide MOS devices that tunneling current changes with gate-oxide thickness. To analyze quantitatively the behaviors of scaled MOS devices in the effects of gate tunneling current and predict the trends, the characteristics of MOS devices are studied in detail using HSPICE simulator. The simulation results in BSIM4 model well agree with the model proposed. The theory and experiment data are contributed to the VLSI circuit design in the future.

Effect of Gate Oxide Thickness Uniformity on the Characteristics of Three-dimensional Transistors

2006 ◽  
Author(s):  
Heung-Jae Cho ◽  
Tae-Yoon Kim ◽  
Yong Soo Kim ◽  
Se-Aug Jang ◽  
Seung Ryong Lee ◽  
...  
Keyword(s):  
Three Dimensional ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Thickness Uniformity ◽  
Gate Oxide Thickness

scholarly journals Some Considerations on Tunneling Losses in Field-Effect Devices for Low-Voltage Microcontrollers

1998 ◽  
Vol 21 (1) ◽  
pp. 57-60 ◽  
Author(s):  
M. A. Grado-Caffaro ◽  
M. Grado-Caffaro
Keyword(s):  
Electric Field ◽  
Oxide Layer ◽  
Power Density ◽  
Field Effect ◽  
Low Voltage ◽  
Tunneling Current ◽  
Oxide Thickness ◽  
High Electric Field ◽  
Floating Gate ◽  
Field Effect Devices

The loss power density associated with the tunneling current in a typical MOS cell with a floating gate is evaluated for high electric-field strengths in the oxide layer. Furthermore, problems related to oxide thickness are discussed.

scholarly journals Threshold voltage roll-off for sub-10 nm asymmetric double gate MOSFET

2019 ◽  
Vol 9 (1) ◽  
pp. 163
Author(s):  
Hakkee Jung
Keyword(s):  
Threshold Voltage ◽  
Tunneling Current ◽  
Gate Oxide ◽  
Oxide Thickness ◽  
Channel Length ◽  
Double Gate ◽  
Short Channel ◽  
Double Gate Mosfet ◽  
Channel Effects ◽  
Channel Thickness

Threshold voltage roll-off is analyzed for sub-10 nm asymmetric double gate (DG) MOSFET. Even asymmetric DGMOSFET will increase threshold voltage roll-off in sub-10 nm channel length because of short channel effects due to the increase of tunneling current, and this is an obstacle against the miniaturization of asymmetric DGMOSFET. Since asymmetric DGMOSFET can be produced differently in top and bottom oxide thickness, top and bottom oxide thicknesses will affect the threshold voltage roll-off. To analyze this, <em>thermal</em><em> </em>emission current and tunneling current have been calculated, and threshold voltage roll-off by the reduction of channel length has been analyzed by using channel thickness and top/bottom oxide thickness as parameters. As a result, it is found that, in short channel asymmetric double gate MOSFET, threshold voltage roll-off is changed greatly according to top/bottom gate oxide thickness, and that threshold voltage roll-off is more influenced by silicon thickness. In addition, it is found that top and bottom oxide thickness have a relation of inverse proportion mutually for maintaining identical threshold voltage. Therefore, it is possible to reduce the leakage current of the top gate related with threshold voltage by increasing the thickness of the top gate oxide while maintaining the same threshold voltage.

Cross-Sectional TEM Study of Three-Dimensional MOS Devices

1987 ◽  
Vol 107 ◽  
Author(s):  
Kyung-Ho Park ◽  
T. Sasaki ◽  
T. Iwai ◽  
M. Hasegawa ◽  
N. Sasaki
Keyword(s):  
Electron Microscopy ◽  
Three Dimensional ◽  
Gate Oxide ◽  
Crystal Defects ◽  
Interface Roughness ◽  
Bulk Silicon ◽  
Cross Sectional ◽  
Mos Devices ◽  
Transmission Electron ◽  
20 Nm

AbstractThis paper describes cross-sectional transmission electron microscopy (TEM) observation on finished 3-D MOS devices, fabricated with a laser-recrystallized SOI. The laser-recrystallized SOI contained crystal defects such as micro-twinning, grain boundaries and dislocations. It is also clearly shown that the interface roughness between the gate oxide and SOI is as much as 20 nm height, in where the interface is very smooth between the gate oxide and bulk silicon.

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