Latchup Free Lateral Cmos on Laser Recrystallized Silicon

1985 ◽  
Vol 53 ◽  
Author(s):  
S. Sritharan ◽  
R. Solanki ◽  
G. J. Collins ◽  
J. Fukumoto ◽  
N. Szluk ◽  
...  
Keyword(s):  
Oxide Layer ◽  
Leakage Current ◽  
Silicon Layer ◽  
Channel Length ◽  
Ring Oscillators ◽  
Surface Electron ◽  
Mos Devices ◽  
Thick Oxide Layer ◽  
Subthreshold Leakage ◽  
Nmos Transistors

ABSTRACTLatchup free CMOS devices have been fabricated by forming PMOS transistors in a 0.5μm thick laser recrystallized silicon layer. This recrystallized layer is isolated fram the bulk wafer by a lμm thick oxide layer. The NMOS transistors were fabricated both in the bulk wafer in the region which was used as the recrystallization seeds, as well as in the recrystallized silicon layer itself. Ring oscillators fabricated with 3μm channel length using a bi-layer lateral CMOS structure show a naninal delay of 1.7ns/stage. The MOS devices fabricated in the recrystallized silicon show low subthreshold leakage current, and surface electron and hole mobilities of 580cm2/V.s and 210cm2/V.s respectively.

Circuit Voltage Probe Based on Time-Integrated Measurements of Optical Emission From Leakage Current

2002 ◽  
Author(s):  
Franco Stellari ◽  
Peilin Song ◽  
James C. Tsang ◽  
Moyra K. McManus ◽  
Mark B. Ketchen
Keyword(s):  
Leakage Current ◽  
Voltage Drop ◽  
Optical Emission ◽  
Channel Length ◽  
Operating Conditions ◽  
Power Circuit ◽  
Hot Carrier ◽  
Optical Inspection ◽  
Low Threshold ◽  
Circuit Power

Abstract Hot-carrier luminescence emission is used to diagnose the cause of excess quiescence current, IDDQ, in a low power circuit implemented in CMOS 7SF technology. We found by optical inspection of the chip that the high IDDQ is related to the low threshold, Vt, device process and in particular to transistors with minimum channel length (0.18 μm). In this paper we will also show that it is possible to gain knowledge regarding the operating conditions of the IC from the analysis of optical emission due to leakage current, aside from simply locating defects and failures. In particular, we will show how it is possible to calculate the voltage drop across the circuit power grid from time-integrated acquisitions of leakage luminescence.

Study on Light Induced Leakage Current Related to Amorphous Silicon TFT Design

2007 ◽  
Vol 124-126 ◽  
pp. 259-262
Author(s):  
Jae Hong Jeon ◽  
Kang Woong Lee
Keyword(s):  
Thin Film ◽  
Amorphous Silicon ◽  
Leakage Current ◽  
Thin Film Transistor ◽  
Silicon Layer ◽  
Gate Electrode ◽  
Silicon Thin Film ◽  
Pattern Design ◽  
Conventional Design ◽  
The One

We investigated the effect of amorphous silicon pattern design regarding to light induced leakage current in amorphous silicon thin film transistor. In addition to conventional design, where amorphous silicon layer is protruding outside the gate electrode, we designed and fabricated amorphous silicon thin film transistors in another two types of bottom gated structure. The one is that the amorphous silicon layer is located completely inside the gate electrode and the other is that the amorphous silicon layer is protruding outside the gate electrode but covered completely by the source and drain electrode. Measurement of the light induced leakage current caused by backlight revealed that the design where the amorphous silicon is located inside the gate electrode was the most effective however the last design was also effective in reducing the leakage current about one order lower than that of the conventional design.

scholarly journals 3D Double Gate FinFET Construction of 30 nm Technology Node Impact Towards Short Channel Effect

2018 ◽  
Vol 12 (3) ◽  
pp. 1358
Author(s):  
Ameer F. Roslan ◽  
F. Salehuddin ◽  
A.S. M.Zain ◽  
K.E. Kaharudin ◽  
H. Hazura ◽  
...  
Keyword(s):  
Leakage Current ◽  
Electrical Characterization ◽  
Channel Length ◽  
Double Gate ◽  
Short Channel ◽  
3D Design ◽  
Drive Current ◽  
Minimum Requirement ◽  
Technology Roadmap ◽  
Low Performance

<p>This paper presents an investigation on properties of Double Gate FinFET (DGFinFET) and impact of physical properties of FinFET towards short channel effects (SCEs) for 30 nm device, where depletion-layer widths of the source-drain corresponds to the channel length aside from constant fin height (HFIN) and the fin thickness (TFIN). Virtual fabrication process of 3-dimensional (3D) design is applied throughout the study and its electrical characterization is employed and substantial is shown towards the FinFET design whereby in terms of the ratio of drive current against the leakage current (ION/IOFF ratio) at 563138.35 compared to prediction made by the International Technology Roadmap Semiconductor (ITRS) 2013. Conclusively, the incremental in ratio has fulfilled the desired in incremental on the drive current as well as reductions of the leakage current. Threshold voltage (VTH) meanwhile has also achieved the nominal requirement predicted by the International Technology Roadmap Semiconductor (ITRS) 2013 for which is at 0.676±12.7% V. The ION , IOFF and VTH obtained from the device has proved to meet the minimum requirement by ITRS 2013 for low performance Multi-Gate technology.</p>

Differential Aging Sensor Using Subthreshold Leakage Current to Detect Recycled ICs

2021 ◽  
pp. 1-12
Author(s):  
Turki Alnuayri ◽  
Saqib Khursheed ◽  
Antonio Leonel Hernandez Martinez ◽  
Daniele Rossi
Keyword(s):  
Leakage Current ◽  
Subthreshold Leakage

Ellipsometric and XPS Studies of 4H-SiC/SiO2 Interfaces, and Sacrificial Oxide Stripped 4H-SiC Surfaces

2006 ◽  
Vol 527-529 ◽  
pp. 1027-1030 ◽  
Author(s):  
Owen J. Guy ◽  
L. Chen ◽  
G. Pope ◽  
K.S. Teng ◽  
T. Maffeis ◽  
...  
Keyword(s):  
Photoelectron Spectroscopy ◽  
Interfacial Layer ◽  
Oxidation Process ◽  
Silicon Layer ◽  
Subsequent Removal ◽  
X Ray ◽  
Mos Devices ◽  
Device Processing ◽  
Form Features ◽  
Silicon Oxygen

The investigation of the silicon carbide surface after a sacrificial silicon oxidation technique is reported. Oxidation of SiC is a necessary step in the fabrication of MOS devices and device termination features such as field plates. Device processing requires the etching of windows through the oxide layer to form features such as metal / SiC contacts. However, this work indicates that a thin interfacial Si-O-C layer is still present after etching the oxide with hydrofluric acid (HF). Ellipsometry and X-ray photoelectron spectroscopy (XPS) have been used to evaluate this interfacial layer formed after oxide growth and after subsequent removal of oxide layers. An XPS analysis of the surface after removal of the oxide revealed that silicon, oxygen and carbon were all present in the remaining layer, which could not be removed by annealing at temperatures up to 1000°C. The Si-O-C layer could be eliminated by altering the oxidation conditions or by using a sacrificial silicon layer oxidation process. Ni Schottky barrier diodes fabricated on the 4H-SiC surface after removal of the oxide, displayed slightly higher ideality factors than those of diodes fabricated on untreated 4H-SiC samples.

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